Yield analysis of a novel wafer manipulation method in 3D stacking. - Bei Zhang; Baohu Li; Vishwani D. Agrawal (3DIC, 2013)

Adopting multi-valued logic for reduced pin-count testing. - Baohu Li; Bei Zhang; Vishwani D. Agrawal (LATS, 2015)

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. - Baohu Li; Vishwani D. Agrawal (NATW, 2015)

Applications of Mixed-Signal Technology in Digital Testing. - Baohu Li; Vishwani D. Agrawal (J. Electron. Test., 2016)