A cache memory with unit tile and line accessibility. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (ICIS, 2016)

Tile/line access cache memory based on a multi-level Z-order tiling data layout. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (Concurr. Comput. Pract. Exp., 2018)