A dependence graph-based approach to the design of algorithm-based fault tolerant systems. - Bapiraju Vinnakota; Niraj K. Jha (FTCS, 1990)

MACHETE: synthesis of sequential machines for easy testability. - Bapiraju Vinnakota; Niraj K. Jha (EURO-DAC, 1991)

Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. - Bapiraju Vinnakota; Niraj K. Jha (FTCS, 1991)

Repair of RAMs With Clustered Faults. - Bapiraju Vinnakota; Jason Andrews (ICCD, 1992)

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Computers, 1993)

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1993)

Functional Test Generation for FSMs by Fault Extraction. - Bapiraju Vinnakota; Jason Andrews (DAC, 1994)

The Design of Analog Self-Checking Circuits. - Bapiraju Vinnakota; Ramesh Harjani (VLSI Design, 1994)

Analog circuit observer blocks. - Ramesh Harjani; Bapiraju Vinnakota (VTS, 1994)

Enumeration of Binary Trees. - Bapiraju Vinnakota; V. V. Bapeswara Rao (Inf. Process. Lett., 1994)

Generation of All Reed-Muller Expansions of a Switching Function. - Bapiraju Vinnakota; V. V. Bapeswara Rao (IEEE Trans. Computers, 1994)

Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1994)

A C-testable carry-free divider. - Hosahalli R. Srinivas; Bapiraju Vinnakota; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Reducing test application time in scan design schemes. - Bapiraju Vinnakota; Nicholas J. Stessman (VTS, 1995)

Implementing Multiplication with Split Read-Only Memory. - Bapiraju Vinnakota (IEEE Trans. Computers, 1995)

Zamlog: a parallel algorithm for fault simulation based on Zambezi. - Minesh B. Amin; Bapiraju Vinnakota (ICCAD, 1996)

Mixed-Signal Design for Test. - Bapiraju Vinnakota; Ramesh Harjani (VLSI Design, 1996)

ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. - Minesh B. Amin; Bapiraju Vinnakota (VTS, 1996)

System-level design for test of fully differential analog circuits. - Nicholas J. Stessman; Bapiraju Vinnakota; Ramesh Harjani (IEEE J. Solid State Circuits, 1996)

Pseudoduplication - An ACOB Technique for Single-Ended Circuits. - Bapiraju Vinnakota; Ramesh Harjani; Wooyoung Choi (VLSI Design, 1997)

Workload Distribution in Fault Simulation. - Minesh B. Amin; Bapiraju Vinnakota (J. Electron. Test., 1997)

Monitoring Power Dissipation for Fault Detection. - Bapiraju Vinnakota (J. Electron. Test., 1997)

Fast State Verification. - Dechang Sun; Bapiraju Vinnakota; Wanli Jiang (DAC, 1998)

Process-tolerant test with energy consumption ratio. - Bapiraju Vinnakota; Wanli Jiang; Dechang Sun (ITC, 1998)

Fast fault translation. - Bapiraju Vinnakota; Jason Andrews (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Digital detection of parametric faults in data converters. - Bapiraju Vinnakota; Ramesh Harjani (CICC, 1999)

Digital Aetection of Analog Parametric Faults in SC Filters. - Ramesh Harjani; Bapiraju Vinnakota (DAC, 1999)

Deep submicron defect detection with the energy consumption ratio. - Bapiraju Vinnakota (ICCAD, 1999)

Statistical threshold formulation for dynamic I_dd test. - Wanli Jiang; Bapiraju Vinnakota (ITC, 1999)

Data parallel fault simulation. - Minesh B. Amin; Bapiraju Vinnakota (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Optimal test-set generation for parametric fault detection in switched capacitor filters. - Wooyoung Choi; Ramesh Harjani; Bapiraju Vinnakota (Asian Test Symposium, 2000)

Fast Test Application Technique Without Fast Scan Clocks. - Seonki Kim; Bapiraju Vinnakota (ICCAD, 2000)

An analysis of the delay defect detection capability of the ECR test method. - Seonki Kim; Sreejit Chakravarty; Bapiraju Vinnakota (ITC, 2000)

Biomedical ICs: What is Different about Testing those ICs? - Bapiraju Vinnakota; André Ivanov (VTS, 2000)

IC test using the energy consumption ratio. - Wanli Jiang; Bapiraju Vinnakota (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

DFT for digital detection of analog parametric faults in SC filters. - Bapiraju Vinnakota; Ramesh Harjani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Crosstalk Fault Detection by Dynamic Idd. - Xiaoyun Sun; Seonki Kim; Bapiraju Vinnakota (ICCAD, 2001)

High Performance Parallel Fault Simulation. - Amit K. Varshney; Bapiraju Vinnakota; Eric Skuldt; Brion L. Keller (ICCD, 2001)

Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. - Wooyoung Choi; Ramesh Harjani; Bapiraju Vinnakota (ISCAS (1), 2001)

Current Measurement for Dynamic Idd Test. - Xiaoyun Sun; Bapiraju Vinnakota (VTS, 2001)

Defect-oriented test scheduling. - Wanli Jiang; Bapiraju Vinnakota (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Statistical threshold formulation for dynamic Idd test. - Wanli Jiang; Bapiraju Vinnakota (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Test Vector Generation Based on Correlation Model for Ratio-Iddq. - Xiaoyun Sun; Larry L. Kinney; Bapiraju Vinnakota (ITC, 2003)

Development of Energy Consumption Ratio Test. - Xiaoyun Sun; Larry L. Kinney; Bapiraju Vinnakota (VTS, 2003)

A digital DFT technique for verifying the static performance of A/D converters. - Wooyoung Choi; Bapiraju Vinnakota; Ramesh Harjani (CICC, 2004)

Combining dictionary coding and LFSR reseeding for test data compression. - Xiaoyun Sun; Larry L. Kinney; Bapiraju Vinnakota (DAC, 2004)

Towards an Energy-Star WLAN Infrastructure. - Amit P. Jardosh; Gianluca Iannaccone; Konstantina Papagiannaki; Bapi Vinnakota (HotMobile, 2007)

Green WLANs: On-Demand WLAN Infrastructures. - Amit P. Jardosh; Konstantina Papagiannaki; Elizabeth M. Belding; Kevin C. Almeroth; Gianluca Iannaccone; Bapi Vinnakota (Mob. Networks Appl., 2009)

Panel: Reliability of data centers: Hardware vs. software. - Mehdi Baradaran Tahoori; Ishwar Parulkar; Dan Alexandrescu; Kevin Granlund; Allan Silburt; Bapi Vinnakota (DATE, 2010)

A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication. - Ramin Farjadrad; Bapiraju Vinnakota (Hot Interconnects, 2019)

High Capacity On-Package Physical Link Considerations. - Greg Taylor; Ramin Farjadrad; Bapiraju Vinnakota (Hot Interconnects, 2019)

Bunch of Wires: An Open Die-to-Die Interface. - Shahab Ardalan; Halil Cirit; Ramin Farjad-Rad; Mark Kuemerle; Ken Poulton; Suresh Subramanian; Bapiraju Vinnakota (Hot Interconnects, 2020)

Special Session: Test Challenges in a Chiplet Marketplace. - Marc Hutner; R. Sethuram; Bapi Vinnakota; Dave Armstrong; A. Copperhall (VTS, 2020)

A Bunch-of-Wires (BoW) Interface for Interchiplet Communication. - Ramin Farjadrad; Mark Kuemerle; Bapi Vinnakota (IEEE Micro, 2020)

The Open Domain-Specific Architecture: Next Steps to Production. - Bapiraju Vinnakota (NANOCOM, 2021)

The Open Domain-Specific Architecture: An Introduction (Invited). - Bapi Vinnakota (SLIP, 2021)

An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW). - Shahab Ardalan; Ramin Farjadrad; Mark Kuemerle; Ken Poulton; Suresh Subramaniam; Bapiraju Vinnakota (IEEE Micro, 2021)

The Open Domain-Specific Architecture. - Bapiraju Vinnakota; Ishwar Agarwal; Kevin Drucker; Dharmesh Jani; Gary Miller; Millind Mittal; Robert Wang 005 (IEEE Micro, 2021)

SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP). - Vivek Raghunathan; Karl Muth; Bapiraju Vinnakota; Prasad Venugopal; Rebecca Schaevitz; Manish Mehta 005 (ISQED, 2022)

IP Session on Chiplet: Design, Assembly, and Test. - Bapi Vinnakota; Jaber Derakhshandeh; Eric Beyne; Erik Jan Marinissen; Sreejit Chakravarty (VTS, 2023)

Modular High-Performance Computing Using Chiplets. - Bapi Vinnakota; John M. Shalf (Comput. Sci. Eng., 2023)