Fast CMOS ECL receivers with 100-mV worst-case sensitivity. - Barbara A. Chappell; Terry I. Chappell; Stanley E. Schuster; Hermann M. Segmuller; James W. Allan; Robert L. Franch; Phillip J. Restle (IEEE J. Solid State Circuits, 1988)

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces. - Terry I. Chappell; Stanley E. Schuster; Barbara A. Chappell; James W. Allan; Jack Y.-C. Sun; Stephen P. Klepner; Robert L. Franch; Paul F. Greier; Phillip J. Restle (IEEE J. Solid State Circuits, 1989)

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. - Terry I. Chappell; Barbara A. Chappell; Stanley E. Schuster; James W. Allan; Stephen P. Klepner; Rajiv V. Joshi; Robert L. Franch (IEEE J. Solid State Circuits, 1991)

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM. - Stanley E. Schuster; Terry I. Chappell; Barbara A. Chappell; Robert L. Franch (IEEE J. Solid State Circuits, 1992)

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. - Ghavam G. Shahidi; James D. Warnock; James Comfort; Stephen E. Fischer; Patricia A. McFarland; Alexandre Acovic; Terry I. Chappell; Barbara A. Chappell; Tak H. Ning; Carl J. Anderson; Robert H. Dennard; Jack Y.-C. Sun; et al. (IBM J. Res. Dev., 1995)

Static timing analysis for self resetting circuits. - Vinod Narayanan; Barbara A. Chappell; Bruce M. Fleischer (ICCAD, 1996)

A Constructive Matching Algorithm for Library-Based Domino Technology Mapping. - Xinning Wang; Prashant Sawkar; Barbara A. Chappell (IWLS, 2002)