Balanced $(3+2 log n) Delta G$ Adders for Moduli Set $ {{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1 }$. - Ghassem Jaberipur; Bardia Nadimi (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Mining SoC Message Flows with Attention Model. - Md Rubel Ahmed; Bardia Nadimi; Hao Zheng 001 (CoRR, 2022)

System-on-Chip Message Flow Mining with Masked-Language Models. - Md Rubel Ahmed; Bardia Nadimi; Hao Zheng 001 (MWSCAS, 2023)

A Multi-Expert Large Language Model Architecture for Verilog Code Generation. - Bardia Nadimi; Hao Zheng 001 (CoRR, 2024)

Modulo-(22n+1) Arithmetic via Two Parallel n-bit Residue Channels. - Ghassem Jaberipur; Bardia Nadimi; Jeong-A Lee (CoRR, 2024)

Inferring Message Flows From System Communication Traces. - Bardia Nadimi; Hao Zheng 001 (CoRR, 2024)

Forward and Reverse Converters for the Moduli-Set {22q+1,2q+2q-1± 1}. - Ghassem Jaberipur; Bardia Nadimi; R. Kazemi; Jeong-A Lee (CoRR, 2024)

PyraNet: A Large Scale Hierarchical Verilog Dataset. - Bardia Nadimi; Ghali Omar Boutaib; Hao Zheng 001 (CoRR, 2024)

AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs. - Md Rubel Ahmed; Bardia Nadimi; Hao Zheng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

AutoFlows: Inferring Message Flows from System Communication Traces. - Bardia Nadimi; Hao Zheng 001 (ISQED, 2025)

VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric. - Bardia Nadimi; Ghali Omar Boutaib; Hao Zheng 001 (CoRR, 2025)