A time-domain latch interpolation technique for low power flash ADCs. - Jong-In Kim; Wan Kim; Barosaim Sung; Seung-Tak Ryu (CICC, 2011)

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. - Hyeok-Ki Hong; Hyun-Wook Kang; Barosaim Sung; Choong-Hoon Lee; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2013)

A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS. - Barosaim Sung; Chilun Lo; Jaehoon Lee 005; Sangdon Jung; Seungjin Kim; Jaehong Jung; Seungyong Bae; Youngsea Cho; Yong Lim; Dooseok Choi; Myeongcheol Shin; Soonwoo Choi; et al. (A-SSCC, 2019)

An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators. - Jaehoon Lee 005; Yong Lim; Barosaim Sung; Seunghyun Oh; Jung-Hoon Chun; Jongwoo Lee (ISCAS, 2020)

A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (ISSCC, 2022)

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (IEEE J. Solid State Circuits, 2022)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)