Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits. - Abhijit Chatterjee; Sabyasachi Deyati; Barry John Muldrey; Shyam Kumar Devarakond; Aritra Banerjee (ICCAD, 2012)

VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests. - Sabyasachi Deyati; Aritra Banerjee; Barry John Muldrey; Abhijit Chatterjee (VLSI Design, 2013)

RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning. - Barry John Muldrey; Sabyasachi Deyati; Michael Giardino; Abhijit Chatterjee (VTS, 2013)

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. - Sabyasachi Deyati; Barry John Muldrey; Adit D. Singh; Abhijit Chatterjee (ATS, 2014)

Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operation. - Debashis Banerjee; Barry John Muldrey; Shreyas Sen; Xian Wang 003; Abhijit Chatterjee (ICCAD, 2014)

Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. - Sabyasachi Deyati; Barry John Muldrey; Aritra Banerjee; Abhijit Chatterjee (VTS, 2014)

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. - Sabyasachi Deyati; Barry John Muldrey; Adit D. Singh; Abhijit Chatterjee (ATS, 2015)

Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware. - Nicholas Tzou; Debesh Bhatta; Barry J. Muldrey; Thomas Moon; Xian Wang 003; Hyun Woo Choi; Abhijit Chatterjee (J. Electron. Test., 2015)

Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits. - Barry John Muldrey; Sabyasachi Deyati; Abhijit Chatterjee (ATS, 2016)

Trojan detection in digital systems using current sensing of pulse propagation in logic gates. - Sabyasachi Deyati; Barry John Muldrey; Abhijit Chatterjee (ISQED, 2016)

DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems. - Barry John Muldrey; Sabyasachi Deyati; Abhijit Chatterjee (ITC, 2016)

TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. - Sabyasachi Deyati; Barry John Muldrey; Abhijit Chatterjee (VLSID, 2016)

Adaptive testing of analog/RF circuits using hardware extracted FSM models. - Sabyasachi Deyati; Barry John Muldrey; Abhijit Chatterjee (VTS, 2016)

Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus. - Nicholas Tzou; Debesh Bhatta; Xian Wang 003; Te-Hui Chen; Sen-Wen Hsiao; Barry J. Muldrey; Hyun Woo Choi; Abhijit Chatterjee (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. - Sabyasachi Deyati; Barry John Muldrey; Abhijit Chatterjee (DATE, 2017)

Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. - Sabyasachi Deyati; Barry J. Muldrey; Byunghoo Jung; Abhijit Chatterjee (ITC, 2017)

Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. - Barry John Muldrey; Sabyasachi Deyati; Abhijit Chatterjee (VLSID, 2017)

Self-Learning RF Receiver Systems: Process Aware Real-Time Adaptation to Channel Conditions for Low Power Operation. - Debashis Banerjee; Barry John Muldrey; Xian Wang 003; Shreyas Sen; Abhijit Chatterjee (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery. - Barry John Muldrey; Suvadeep Banerjee; Abhijit Chatterjee (VTS, 2019)

Algorithms for Post-silicon Validation and Debug of Radio-frequency, analog, and mixed-signal Circuits and Systems. - Barry John Muldrey (2019)

Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware. - Sabyasachi Deyati; Barry J. Muldrey; Abhijit Chatterjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps. - Partha Sarathi Paul 002; Maisha Sadia; Md Razuan Hossain; Barry J. Muldrey; Md Sakib Hasan (ACM Great Lakes Symposium on VLSI, 2021)

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range. - Partha Sarathi Paul 002; Anurag Dhungel; Maisha Sadia; Md Razuan Hossain; Barry John Muldrey; Md Sakib Hasan (ICECS, 2021)

Design and Application of a Novel 4-Transistor Chaotic Map with Robust Performance. - Maisha Sadia; Partha Sarathi Paul 002; Md Razuan Hossain; Barry J. Muldrey; Md Sakib Hasan (ICECS, 2021)

High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. - Sabyasachi Deyati; Barry J. Muldrey; Adit D. Singh; Abhijit Chatterjee (J. Electron. Test., 2021)

Toward the creation of a novel electric bike rental program to ease university congestion. - Jacob Barnes; Barry John Muldrey; Charles Walter (ACM Southeast Regional Conference, 2022)

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design. - Partha Sarathi Paul 002; Maisha Sadia; Md Razuan Hossain; Barry J. Muldrey; Md Sakib Hasan (IEEE Access, 2022)

Robust Chaos With Novel 4-Transistor Maps. - Maisha Sadia; Partha Sarathi Paul 002; Md Razuan Hossain; Barry John Muldrey; Md Sakib Hasan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems. - Sabyasachi Deyati; Barry John Muldrey; Abhijit Chatterjee (J. Electron. Test., 2023)