Memory-CPU Size Optimization for Embedded System Designs. - Barry Shackleford; Mitsuhiro Yasuda; Etsuko Okushi; Hisao Koizumi; Hiroyuki Tomiyama; Hiroto Yasuura (DAC, 1997)

A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. - Barry Shackleford; Etsuko Okushi; Mitsuhiro Yasuda; Hisao Koizumi; Katsuhiko Seo; Takashi Iwamoto; Hiroto Yasuura (ICONIP (1), 1997)

A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture. - Mitsuhiro Yasuda; Katsuhiko Seo; Hisao Koizumi; Barry Shackleford; Fumio Suzuki (ASP-DAC, 1998)

An FPGA-based genetic algorithm machine (poster abstract). - Barry Shackleford; Etsuko Okushi; Mitsuhiro Yasuda; Hisao Koizumi; Katsuhiko Seo; Takashi Iwamoto; Hiroto Yasuura (FPGA, 2000)

Attacking the semantic gap between application programming languages and configurable hardware. - Greg Snider; Barry Shackleford; Richard J. Carter (FPGA, 2001)

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. - Barry Shackleford; Greg Snider; Richard J. Carter; Etsuko Okushi; Mitsuhiro Yasuda; Katsuhiko Seo; Hiroto Yasuura (Genet. Program. Evolvable Mach., 2001)

High-Performance Cellular Automata Random Number Generators for Embedded Probabilistic Computing Systems. - Barry Shackleford; Motoo Tanaka; Richard J. Carter; Greg Snider (Evolvable Hardware, 2002)

FPGA implementation of neighborhood-of-four cellular automata random number generators. - Barry Shackleford; Motoo Tanaka; Richard J. Carter; Greg Snider (FPGA, 2002)

Random Number Generators Implemented with Neighborhood-of-Four, Non-locally Connected Cellular Automata. - Barry Shackleford; Motoo Tanaka; Richard J. Carter; Greg Snider (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)