Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM. - Pavel Poliakov; Ankur Anchlia; Marie Garcia Bardon; Bram Rooseleer; Bart De Wachter; Nadine Collaert; Koen van der Zanden; Wim Dehaene; Diederik Verkest; Miguel Corbalan Miranda (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

Vesuvius-3D: A 3D-DfT demonstrator. - Erik Jan Marinissen; Bart De Wachter; Stephen O'Loughlin; Sergej Deutsch; Christos Papameletis; Tobias Burgherr (ITC, 2014)

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. - Erik Jan Marinissen; Bart De Wachter; Ken Smith; Jorg Kiesewetter; Mottaqiallah Taouil; Said Hamdioui (ITC, 2014)

Automated testing of bare die-to-die stacks. - Erik Jan Marinissen; Bart De Wachter; Teng Wang; Jens Fiedler; Jorg Kiesewetter; Karsten Stoll (ITC, 2015)

A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards. - Erik Jan Marinissen; Ferenc Fodor; Bart De Wachter; Jorg Kiesewetter; Eric Hill; Ken Smith (ITC-Asia, 2017)