Fast Prolog with an Extended General Purpose Architecture. - Bruce K. Holmer; Barton Sano; Michael J. Carlton; Peter Van Roy; Ralph Clarke Haygood; William R. Bush; Alvin M. Despain; Joan M. Pendleton; Tep P. Dobry (ISCA, 1990)

The 16-fold way: a microparallel taxonomy. - Barton Sano; Alvin M. Despain (MICRO, 1993)

190-MHz CMOS 4-Kbyte Pipelined Caches. - Apoorv Srivastava; Yong-Seon Koh; Barton Sano; Alvin M. Despain (ISCAS, 1995)

Design and Analysis of Hardware for High-Performance Prolog. - Bruce K. Holmer; Barton Sano; Michael J. Carlton; Peter Van Roy; Alvin M. Despain (J. Log. Program., 1996)

Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. - Chia-Lin Yang; Barton Sano; Alvin R. Lebeck (MICRO, 1998)

Piranha: a scalable architecture based on single-chip multiprocessing. - Luiz André Barroso; Kourosh Gharachorloo; Robert McNamara; Andreas Nowatzyk; Shaz Qadeer; Barton Sano; Scott Smith; Robert Stets; Ben Verghese (ISCA, 2000)

Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. - Chia-Lin Yang; Barton Sano; Alvin R. Lebeck (IEEE Trans. Computers, 2000)