VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. - Basant K. Mohanty; Pramod Kumar Meher (APCCAS, 2006)

Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. - Basant K. Mohanty; Pramod Kumar Meher (APCCAS, 2006)

Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. - Basant K. Mohanty; Pramod Kumar Meher (ASAP, 2008)

Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. - Basant K. Mohanty; Pramod Kumar Meher (ASAP, 2008)

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. - Pramod Kumar Meher; Basant K. Mohanty; Jagdish Chandra Patra (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic. - Anurag Mahajan; Basant K. Mohanty (APCCAS, 2010)

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2010)

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2011)

Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2011)

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. - Basant K. Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal (ISCAS, 2012)

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. - Basant K. Mohanty; Anurag Mahajan; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank. - Basant K. Mohanty; Somaya Al-Máadeed; Abbes Amira (IDT, 2013)

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer. - Basant K. Mohanty; Anurag Mahajan (IET Circuits Devices Syst., 2013)

Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT. - Basant K. Mohanty; Anurag Mahajan (J. Low Power Electron., 2013)

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2013)

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2013)

Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. - Pramod Kumar Meher; Basant K. Mohanty; Thambipillai Srikanthan (ISCAS, 2014)

Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier. - Basant K. Mohanty; Vikas Tiwari (Circuits Syst. Signal Process., 2014)

Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. - Basant K. Mohanty; Pramod Kumar Meher (IET Image Process., 2014)

Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. - Basant K. Mohanty; Pramod Kumar Meher; Somaya Al-Máadeed; Abbes Amira (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Area-Delay-Power Efficient Carry-Select Adder. - Basant Kumar Mohanty; Sujit Kumar Patel (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Efficient Integer DCT Architectures for HEVC. - Pramod Kumar Meher; Sang Yoon Park; Basant Kumar Mohanty; Khoon Seong Lim; Chuohao Yeo (IEEE Trans. Circuits Syst. Video Technol., 2014)

Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems. - Vivek Chaturvedi; Basant K. Mohanty; Thambipillai Srikanthan (DSP, 2015)

Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems. - Basant K. Mohanty; Vivek Chaturvedi; Vijeta Rathore; Thambipillai Srikanthan (DSP, 2015)

FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications. - Carlo Safarian; Tokunbo Ogunfunmi; Walter J. Kozacky; Basant K. Mohanty (DSP, 2015)

Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. - Basant K. Mohanty; Pramod Kumar Meher; Thambipillai Srikanthan (ISCAS, 2015)

Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. - Pramod Kumar Meher; Basant Kumar Mohanty; M. N. S. Swamy (VLSID, 2015)

Efficient very large-scale integration architecture for variable length block least mean square adaptive filter. - Basant Kumar Mohanty; Sujit Kumar Patel (IET Signal Process., 2015)

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. - Pramod Kumar Meher; Basant Kumar Mohanty; Sujit Kumar Patel; Soumya Ganguly; Thambipillai Srikanthan (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. - Basant Kumar Mohanty (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. - Hassan Rabah; Abbes Amira; Basant Kumar Mohanty; Somaya Al-Máadeed; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer. - Basant Kumar Mohanty; Subodh Kumar Singhal (Circuits Syst. Signal Process., 2016)

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. - Basant Kumar Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal; M. N. S. Swamy (Integr., 2016)

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic. - Subodh Kumar Singhal; Basant Kumar Mohanty (J. Circuits Syst. Comput., 2016)

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. - Basant Kumar Mohanty; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2016)

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. - Basant K. Mohanty; Pramod Kumar Meher; Sujit Kumar Patel (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT. - Basant Kumar Mohanty; Abhishek Choubey (Circuits Syst. Signal Process., 2017)

Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers. - Basant Kumar Mohanty; Gaurav Singh; Ganapati Panda (Circuits Syst. Signal Process., 2017)

Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT. - Abhishek Choubey; Basant Kumar Mohanty (Circuits Syst. Signal Process., 2018)

Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids. - Vasundhara; Basant Kumar Mohanty; Ganapati Panda; Niladri B. Puhan (Circuits Syst. Signal Process., 2018)

Efficient Fixed-Width Adder-Tree Design. - Basant Kumar Mohanty (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. - Subodh Kumar Singhal; Basant K. Mohanty; Sujit Kumar Patel; Gaurav Saxena (J. Circuits Syst. Comput., 2020)

Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform. - Basant Kumar Mohanty (IEEE Trans. Circuits Syst. Video Technol., 2020)

An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. - Basant Kumar Mohanty; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Chronic kidney disease stage identification using texture analysis of ultrasound images. - Rehan Ahmad; Basant K. Mohanty (Biomed. Signal Process. Control., 2021)

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding. - Basant Kumar Mohanty (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage. - Rehan Ahmad; Basant K. Mohanty (Turkish J. Electr. Eng. Comput. Sci., 2023)

Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors. - Basant Kumar Mohanty (IEEE Trans. Very Large Scale Integr. Syst., 2024)