An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing. - Christian Schuck; Bastian Haetzer; Jürgen Becker 001 (Int. J. Reconfigurable Comput., 2009)

Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. - Christian Schuck; Bastian Haetzer; Jürgen Becker 001 (ReCoSoC, 2010)

Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. - Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh; Martin Radetzki (WESE, 2011)

A case study on message-based discrete event simulation for Transaction Level Modeling. - Bastian Haetzer; Martin Radetzki (FDL, 2011)

Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs. - Christian Schuck; Bastian Haetzer; Michael Hübner 001; Jürgen Becker 001 (IPDPS Workshops, 2011)

Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. - Christian Schuck; Bastian Haetzer; Jürgen Becker 001 (Int. J. Reconfigurable Comput., 2011)

Systemc transaction level modeling with transaction events. - Bastian Haetzer; Martin Radetzki (FDL, 2013)

A comparison of parallel systemc simulation approaches at RTL. - Bastian Haetzer; Martin Radetzki (FDL, 2014)

Asynchronous parallel simulation with transaction events. - Bastian Haetzer; Martin Radetzki (ICSAMOS, 2014)