A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. - Bastien Giraud; Amara Amara; Andrei Vladimirescu (ISCAS, 2007)

Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. - Bastien Giraud; Amara Amara (DELTA, 2008)

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. - Piotr Nasalski; Adam Makosiej; Bastien Giraud; Andrei Vladimirescu; Amara Amara (ICECS, 2008)

A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. - Bastien Giraud; Amara Amara (ISCAS, 2008)

SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. - Piotr Nasalski; Adam Makosiej; Bastien Giraud; Andrei Vladimirescu; Amara Amara (ISCAS, 2009)

Technology variability from a design perspective. - Borivoje Nikolic; Bastien Giraud; Zheng Guo; Liang-Teck Pang; Ji-Hoon Park; Seng Oon Toh (CICC, 2010)

An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. - Amara Amara; Bastien Giraud; Olivier Thomas (DELTA, 2010)

Technology Variability From a Design Perspective. - Borivoje Nikolic; Ji-Hoon Park; Jaehwa Kwak; Bastien Giraud; Zheng Guo; Liang-Teck Pang; Seng Oon Toh; Ruzica Jevtic; Kun Qian 014; Costas J. Spanos (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. - Guillaume Moritz; Bastien Giraud; Jean-Philippe Noel; David Turgis; Anuj Grover (ICICDT, 2013)

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. - Bertrand Pelloux-Prayer; Alexandre Valentian; Bastien Giraud; Yvain Thonnart; Jean-Philippe Noel; Philippe Flatresse; Edith Beigné (VLSI-SoC, 2013)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. - Anuj Grover; Promod Kumar; Mohammad Daud; G. S. Visweswaran; Chittoor R. Parthasarathy; Jean-Philippe Noel; David Turgis; Bastien Giraud; Guillaume Moritz (ICICDT, 2015)

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (NVMTS, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture. - Kaya Can Akyel; Henri-Pierre Charles; Julien Mottin; Bastien Giraud; Gregory Suraci; Sébastien Thuries; Jean-Philippe Noel (ICRC, 2016)

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noel; Mathieu Moreau; Jean-Michel Portal (NANOARCH, 2016)

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. - Mahesh Nataraj; Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Pascal Andreas Meinerzhagen; Jean-Michel Portal; Pierre-Emmanuel Gaillardon (ISCAS, 2017)

High density emerging resistive memories: What are the limits? - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (LASCAS, 2017)

Architecture, design and technology guidelines for crosspoint memories. - Alexandre Levisse; Pablo Royer; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (NANOARCH, 2017)

Software platform dedicated for in-memory computing circuit evaluation. - Maha Kooli; Henri-Pierre Charles; Clément Touzet; Bastien Giraud; Jean-Philippe Noël (RSP, 2017)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. - Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Kaya Can Akyel; Melanie Brocard; David Turgis; Edith Beigné (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces. - Maha Kooli; Henri-Pierre Charles; Clément Touzet; Bastien Giraud; Jean-Philippe Noel (DATE, 2018)

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. - Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Mathieu Moreau; Jean-Michel Portal (DCIS, 2018)

Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. - Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Adam Makosiej; Marco Antonio Rios; Eduardo Esmanhotto; Emilien Bourde-Cicé; Mathis Bellet; David Turgis; Edith Beigné (NANOARCH, 2018)

Reliable ReRAM-based Logic Operations for Computing in Memory. - Mathieu Moreau; Eloi Muhr; Marc Bocquet; Hassen Aziza; Jean-Michel Portal; Bastien Giraud; Jean-Philippe Noel (VLSI-SoC, 2018)

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. - Ian O'Connor; Mayeul Cantan; Cédric Marchand 002; Bertrand Vilquin; Stefan Slesazeck; Evelyn T. Breyer; Halid Mulaosmanovic; Thomas Mikolajick; Bastien Giraud; Jean-Philippe Noel; Adrian M. Ionescu; Igor Stolichnov (VLSI-SoC, 2018)

Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM. - Alessandro Grossi; Elisa Vianello; Cristian Zambelli; Pablo Royer; Jean-Philippe Noel; Bastien Giraud; Luca Perniola; Piero Olivo; Etienne Nowak (IEEE Trans. Very Large Scale Integr. Syst., 2018)

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. - Deepak M. Mathew; André Lucas Chinazzo; Christian Weis; Matthias Jung 001; Bastien Giraud; Pascal Vivet; Alexandre Levisse; Norbert Wehn (SAMOS, 2019)

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. - Valentin Gherman; Samuel Evain; Bastien Giraud (DATE, 2020)

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. - Jean-Philippe Noël; Valentin Egloff; Maha Kooli; Roman Gauchi; Jean-Michel Portal; Henri-Pierre Charles; Pascal Vivet; Bastien Giraud (DATE, 2020)

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. - Roman Gauchi; Valentin Egloff; Maha Kooli; Jean-Philippe Noël; Bastien Giraud; Pascal Vivet; Subhasish Mitra; Henri-Pierre Charles (ISLPED, 2020)

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. - Mona Ezzadeen; D. Bosch; Bastien Giraud; Sylvain Barraud; Jean-Philippe Noël; Didier Lattard; Joris Lacord; Jean-Michel Portal; François Andrieu (CoRR, 2020)

Storage Class Memory with Computing Row Buffer: A Design Space Exploration. - Valentin Egloff; Jean-Philippe Noel; Maha Kooli; Bastien Giraud; Lorenzo Ciampolini; Roman Gauchi; César Fuguet Tortolero; Eric Guthmuller; Mathieu Moreau; Jean-Michel Portal (DATE, 2021)

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. - Jean-Philippe Noel; Manuel Pezzin; Jean-Frédéric Christmann; Lorenzo Ciampolini; M. Le Coadou; M. Diallo; Florent Lepin; B. Blampey; Simone Bacles-Min; R. Wacquez; Bastien Giraud (ESSCIRC, 2021)

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. - Mona Ezzadeen; Atreya Majumdar; Marc Bocquet; Bastien Giraud; Jean-Philippe Noël; François Andrieu; Damien Querlioz; Jean-Michel Portal (ESSDERC, 2021)

A Self-referenced and regulated sensing solution for PCM with OTS selector. - J. Gasquez; Bastien Giraud; P. Boivin; Y. Moustapha-Rabault; Vincenzo Della Marca; Jean-Pierre Walder; Jean-Michel Portal (VLSI-SoC, 2021)

A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. - J. Gasquez; Bastien Giraud; P. Boivin; Y. Moustapha-Rabault; Vincenzo Della Marca; Jean-Michel Walder; Jean-Michel Portal (VLSI-SoC (Selected Papers), 2021)

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. - Eduardo Esmanhotto; Tifenn Hirtzlin; Niccolo Castellani; S. Martin; Bastien Giraud; François Andrieu; Jean-François Nodin; Damien Querlioz; Jean-Michel Portal; Elisa Vianello (IRPS, 2022)

An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. - A. Philippe; Lorenzo Ciampolini; A. Philippe; M. Gerbaud; M. Ramirez-Corrales; Valentin Egloff; Bastien Giraud; Jean-Philippe Noël (SLIP, 2022)

Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution. - Maha Kooli; Antoine Heraud; Henri-Pierre Charles; Bastien Giraud; Roman Gauchi; Mona Ezzadeen; Kevin Mambu; Valentin Egloff; Jean-Philippe Noel (ACM J. Emerg. Technol. Comput. Syst., 2022)

Binary ReRAM-based BNN first-layer implementation. - Mona Ezzadeen; Atreya Majumdar; Sigrid Thomas; Jean-Philippe Noël; Bastien Giraud; Marc Bocquet; François Andrieu; Damien Querlioz; Jean-Michel Portal (DATE, 2023)

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Yasser Moursy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Manuel Pezzin; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Maxim Vershkov; et al. (IMW, 2023)

Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems. - Jean-Philippe Noël; Emanuele Valea; Laurent Grenouillet; B. Chapuis; Clément Fisher; A. Recoquillay; Bastien Giraud (VLSI-SoC, 2023)

A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM. - Lucas Rhetat; Jean-Philippe Noel; Bastien Giraud; Laurent Grenouillet; Julie Laguerre; Cédric Marchand 002; Ian O'Connor (VLSI-SoC, 2024)

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Olivier Guille; Maxim Vershkov; Alessandro Bricalli; et al. (IEEE J. Solid State Circuits, 2024)

Relaxation-Aware Programming in RRAM: Evaluating and Optimizing Write Termination. - M. Correa Cueto; Bastien Giraud; M. Drouard; Giuseppe Piccolboni; Gabriel Molas; Gaël Pillonnet (IMW, 2025)

Improving Error Correction with Weak-Bit Information in Resistive Memories. - Valentin Gherman; Giuseppe Piccolboni; Zeev Freidin; Matan Guttman; Amir Regev; Gabriel Molas; Ishai Naveh; Bastien Giraud; Antoine Hebert; Ilan Sever (IOLTS, 2025)

A Dataset Generation Toolbox for Dynamic Security Assessment: On the Role of the Security Boundary. - Bastien Giraud; Lola Charles; Agnes Marjorie Nakiganda; Johanna Vorwerk; Spyros Chatzivasileiadis (CoRR, 2025)