A new dynamic test vector compaction for automatic test pattern generation. - Bechir Ayari; Bozena Kaminska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Automatic test vector generation for mixed-signal circuits. - Bechir Ayari; Naim Ben-Hamida; Bozena Kaminska (ED&TC, 1995)

BDD-FTEST: Fast, Backtrack-Free Test Generator Based on Binary Decision Diagram Representation. - Bechir Ayari; Bozena Kaminska (ISCAS, 1995)

Retiming for BIST-Sequential Circuits. - Samir Lejmi; Bozena Kaminska; Bechir Ayari (ISCAS, 1995)

Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits. - Samir Lejmi; Bozena Kaminska; Bechir Ayari (ITC, 1995)

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. - Samir Lejmi; Bozena Kaminska; Bechir Ayari (VTS, 1995)

Testing of embedded A/D converters in mixed-signal circuit. - Naim Ben-Hamida; Bechir Ayari; Bozena Kaminska (ICCD, 1996)

Test Cycle Count Reduction in a Parallel Scan BIST Environment. - Bechir Ayari; Prab Varma (J. Electron. Test., 2000)