A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals. - Behzad Dehlaghi; Sebastian Magierowski; Leonid Belostotski (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. - Behzad Dehlaghi; Anthony Chan Carusone (CICC, 2015)

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. - Shayan Shahramian; Behzad Dehlaghi; Anthony Chan Carusone (ISSCC, 2016)

A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication. - Behzad Dehlaghi; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 µs. - Shayan Shahramian; Behzad Dehlaghi; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. - Shayan Shahramian; Behzad Dehlaghi; Joshua Liang; Ryan Bespalko; Dustin Dunwell; James Bailey 002; Bo Wang; Alireza Sharif Bakhtiar; Michael O'Farrell; Kerry Tang; Anthony Chan Carusone; David Cassan; et al. (ISSCC, 2019)