A CMOS implementation of current-mode min-max circuits and a sample fuzzy application. - Behzad Mesgarzadeh (FUZZ-IEEE, 2004)

A new mesochronous clocking scheme for synchronization in SoC. - Behzad Mesgarzadeh; Christer Svensson; Atila Alvandpour (ISCAS (2), 2004)

A study of injection locking in ring oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS (6), 2005)

Synchronous latency-insensitive design for multiple clock domain. - Anders Edman; Christer Svensson; Behzad Mesgarzadeh (SoCC, 2005)

1.56 GHz On-chip Resonant Clocking in 130nm CMOS. - Martin Hansson; Behzad Mesgarzadeh; Atila Alvandpour (CICC, 2006)

First-Harmonic Injection-Locked Ring Oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (CICC, 2006)

A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2006)

A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS. - Behzad Mesgarzadeh; Atila Alvandpour (SoCC, 2006)

Jitter Characteristic in Charge Recovery Resonant Clock Distribution. - Behzad Mesgarzadeh; Martin Hansson; Atila Alvandpour (IEEE J. Solid State Circuits, 2007)

A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS. - Behzad Mesgarzadeh; Atila Alvandpour (ESSCIRC, 2008)

Low-Power Low-Jitter Clock Generation and Distribution. - Behzad Mesgarzadeh (2008)

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode. - Behzad Mesgarzadeh; Atila Alvandpour (IEEE J. Solid State Circuits, 2009)

EMI reduction by resonant clock distribution networks. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2010)

A multi-segment clocking scheme to reduce on-chip EMI. - Behzad Mesgarzadeh; Iman Esmaeil Zadeh; Atila Alvandpour (SoCC, 2011)

Reliability challenges in avionics due to silicon aging. - Behzad Mesgarzadeh; Ingemar Söderquist; Atila Alvandpour (DDECS, 2012)

A DLL-based injection-locked frequency synthesizer for WiMedia UWB. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2012)

A Class-D stage with harmonic suppression and DLL-based phase generation. - Jonas Fritzin; Behzad Mesgarzadeh; Atila Alvandpour (MWSCAS, 2012)

A process variation tolerant DLL-based UWB frequency synthesizer. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (MWSCAS, 2012)

A quadrature UWB frequency synthesizer with dynamic settling-time calibration. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2013)

An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS. - Ameya Bhide; Omid Esmailzadeh Najari; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISIC, 2014)

A self-calibration technique for fast-switching frequency-hopped UWB synthesis. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (MIXDES, 2014)

Simultaneous switching noise reduction by resonant clock distribution networks. - Behzad Mesgarzadeh (Integr., 2014)

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)