A 12-b 5-Msample/s two-step CMOS A/D converter. - Behzad Razavi; Bruce A. Wooley (IEEE J. Solid State Circuits, 1992)

Design techniques for high-speed, high-resolution comparators. - Behzad Razavi; Bruce A. Wooley (IEEE J. Solid State Circuits, 1992)

Design techniques for low-voltage high-speed digital bipolar circuits. - Behzad Razavi; Yusuke Ota; Robert G. Swartz (IEEE J. Solid State Circuits, 1994)

A 6 GHz 68 mW BiCMOS phase-locked loop. - Behzad Razavi; JanMye James Sung (IEEE J. Solid State Circuits, 1994)

Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS. - Behzad Razavi; Kwing F. Lee; Ran H. Yan (IEEE J. Solid State Circuits, 1995)

Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology. - Behzad Razavi (IEEE J. Solid State Circuits, 1995)

A 2-GHz, 6-mW BiCMOS frequency synthesizer. - Turgut Aytur; Behzad Razavi (IEEE J. Solid State Circuits, 1995)

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply. - Behzad Razavi (IEEE J. Solid State Circuits, 1995)

A study of phase noise in CMOS oscillators. - Behzad Razavi (IEEE J. Solid State Circuits, 1996)

A 2.5-Gb/s 15-mW clock recovery circuit. - Behzad Razavi (IEEE J. Solid State Circuits, 1996)

Next-Generation RF Circuits and Systems. - Behzad Razavi (ARVLSI, 1997)

Recent advances in RF integrated circuits. - Behzad Razavi (IEEE Commun. Mag., 1997)

A 2-GHz 1.6-mW phase-locked loop. - Behzad Razavi (IEEE J. Solid State Circuits, 1997)

Oscillator jitter due to supply and substrate noise. - Frank Herzel; Behzad Razavi (CICC, 1998)

Architectures and circuits for RF CMOS receivers. - Behzad Razavi (CICC, 1998)

RF IC Design Challenges. - Behzad Razavi (DAC, 1998)

A 900-MHz/1.8-GHz CMOS receiver for dual-band applications. - Stephen Wu 003; Behzad Razavi (IEEE J. Solid State Circuits, 1998)

RF transmitter architectures and circuits. - Behzad Razavi (CICC, 1999)

CMOS technology characterization for analog and RF design. - Behzad Razavi (IEEE J. Solid State Circuits, 1999)

A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications. - Behzad Razavi (IEEE J. Solid State Circuits, 1999)

A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs. - Behzad Razavi (IEEE J. Solid State Circuits, 1999)

A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology. - Seema Butala Anand; Behzad Razavi (CICC, 2000)

A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (CICC, 2000)

Stacked inductors and 1-to-2 transformers in CMOS technology. - Alireza Zolfaghari; Andrew Chan; Behzad Razavi (CICC, 2000)

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology. - Christopher Lam 002; Behzad Razavi (IEEE J. Solid State Circuits, 2000)

An 8-bit 150-MHz CMOS A/D converter. - Yun-Ti Wang; Behzad Razavi (IEEE J. Solid State Circuits, 2000)

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (CICC, 2001)

Design of high-speed circuits for optical communication systems. - Behzad Razavi (CICC, 2001)

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. - Jafar Savoj; Behzad Razavi (DAC, 2001)

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. - Seema Butala Anand; Behzad Razavi (IEEE J. Solid State Circuits, 2001)

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2001)

A 5.2-GHz CMOS receiver with 62-dB image rejection. - Behzad Razavi (IEEE J. Solid State Circuits, 2001)

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. - Jafar Savoj; Behzad Razavi (IEEE J. Solid State Circuits, 2001)

Stacked inductors and transformers in CMOS technology. - Alireza Zolfaghari; Andrew Chan; Behzad Razavi (IEEE J. Solid State Circuits, 2001)

The role of monolithic transmission lines in high-speed integrated circuits. - Behzad Razavi (CICC, 2002)

A noninvasive channel-select filter for a CMOS Bluetooth receiver. - Alireza Zolfaghari; Behzad Razavi (CICC, 2002)

Challenges in the design of high-speed clock and data recovery circuits. - Behzad Razavi (IEEE Commun. Mag., 2002)

Prospects of CMOS technology for high-speed optical communication circuits. - Behzad Razavi (IEEE J. Solid State Circuits, 2002)

Modeling of jitter in bang-bang clock and data recovery circuits. - Jri Lee; Kenneth S. Kundert; Behzad Razavi (CICC, 2003)

A study of injection pulling and locking in oscillators. - Behzad Razavi (CICC, 2003)

RF CMOS transceivers for cellular telephony. - Behzad Razavi (IEEE Commun. Mag., 2003)

A 2-GHz CMOS image-reject receiver with LMS calibration. - Lawrence Der; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology. - Sherif Galal; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

Broadband ESD protection circuits in CMOS technology. - Sherif Galal; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A stabilization technique for phase-locked frequency synthesizers. - Tai-Cheng Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. - Jri Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. - Jafar Savoj; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A 5-GHz direct-conversion CMOS transceiver. - Pengfei Zhang; Thai Nguyen; Christopher Lam 002; Douglas Gambetta; Theerachet Soorapanth; Baohong Cheng; Siegfried Hart; Isaac Sever; Taoufik Bourdi; Andrew (KhongMeng) Tham; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A low-power 2.4-GHz transmitter/receiver CMOS IC. - Alireza Zolfaghari; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs. - Pengfei Zhang; Lawrence Der; Dawei Guo; Isaac Sever; Taoufik Bourdi; Chris Lam 002; Alireza Zolfaghari; Jess Chen; Douglas Gambetta; Baohong Cheng; Sujatha Gower; Siegfi Hart; et al. (CICC, 2004)

40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology. - Sherif Galal; Behzad Razavi (IEEE J. Solid State Circuits, 2004)

Analysis and modeling of bang-bang clock and data recovery circuits. - Jri Lee; Kenneth S. Kundert; Behzad Razavi (IEEE J. Solid State Circuits, 2004)

A 40-GHz frequency divider in 0.18-μm CMOS technology. - Jri Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2004)

A study of injection locking and pulling in oscillators. - Behzad Razavi (IEEE J. Solid State Circuits, 2004)

A comparison of electrical and optical clock networks in nanometer technologies. - Bryan D. Ackland; Behzad Razavi; Larry West (CICC, 2005)

A new receiver architecture for multiple-antenna systems. - Hamid Rafati; Behzad Razavi (CICC, 2005)

Multiband UWB transceivers. - Behzad Razavi; Turgut Aytur; Christopher Lam 002; Fei-Ran Yang 004; Ran-Hong Yan 001; Han-Chang Kang; Cheng-Chung Hsu; Chao-Cheng Lee (CICC, 2005)

Will continued process-node shrinks kill high-performance analog design? - Jafar Savoj; David Rich; Brett Forejt; Peter R. Kinget; Un-Ku Moon; Modest M. Oprysko; Behzad Razavi; Hisashi (Sam) Shichijo; Albert Z. Wang (CICC, 2005)

Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". - Jri Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2005)

A UWB CMOS transceiver. - Behzad Razavi; Turgut Aytur; Christopher Lam 002; Fei-Ran Yang 004; Kuang-Yu (Jason) Li; Ran-Hong (Ran) Yan; Han-Chang Kang; Cheng-Chung Hsu; Chao-Cheng Lee (IEEE J. Solid State Circuits, 2005)

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS. - Pengfei Zhang; Lawrence Der; Dawei Guo; Isaac Sever; Taoufik Bourdi; Christopher Lam 002; Alireza Zolfaghari; Jess Chen; Douglas Gambetta; Baohong Cheng; Sujatha Gowder; Siegfried Hart; et al. (IEEE J. Solid State Circuits, 2005)

Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators. - Khaled Abdelfattah; Behzad Razavi (CICC, 2006)

Mutual Injection Pulling Between Oscillators. - Behzad Razavi (CICC, 2006)

Frequency-Based Measurement of Mismatches Between Small Capacitors. - Ashutosh Verma; Behzad Razavi (CICC, 2006)

A Fully Integrated UWB PHY in 0.13µm CMOS. - Turgut Aytur; Han-Chang Kang; Ravishankar H. Mahadevappa; Mustafa Altintas; Stephan ten Brink; Thanh Diep; Cheng-Chung Hsu; Feng Shi; Fei-Ran Yang 004; Chao-Cheng Lee; Ran-Hong Yan 001; Behzad Razavi (ISSCC, 2006)

A 60-GHz CMOS receiver front-end. - Behzad Razavi (IEEE J. Solid State Circuits, 2006)

Design Considerations for Future RF Circuits. - Behzad Razavi (ISCAS, 2007)

CMOS Transceivers at 60 GHz and Beyond1. - Behzad Razavi (ISCAS, 2007)

An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration. - Cheng-Chung Hsu; Fong-Ching Huang; Chih-Yung Shih; Chen-Chih Huang; Ying-Hsi Lin; Chao-Cheng Lee; Behzad Razavi (ISSCC, 2007)

A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider. - Behzad Razavi (ISSCC, 2007)

Heterodyne Phase Locking: A Technique for High-Frequency Division. - Behzad Razavi (ISSCC, 2007)

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers. - Srikanth Gondi; Behzad Razavi (IEEE J. Solid State Circuits, 2007)

A Receiver Architecture for Dual-Antenna Systems. - Hamid Rafati; Behzad Razavi (IEEE J. Solid State Circuits, 2007)

Heterodyne Phase Locking: A Technique for High-Speed Frequency Division. - Behzad Razavi (IEEE J. Solid State Circuits, 2007)

Phase-locking in wireline systems: Present and future. - Behzad Razavi (CICC, 2008)

A 60GHz CMOS Receiver Using a 30GHz LO. - Ali Parsa; Behzad Razavi (ISSCC, 2008)

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider. - Behzad Razavi (IEEE J. Solid State Circuits, 2008)

A Millimeter-Wave Circuit Technique. - Behzad Razavi (IEEE J. Solid State Circuits, 2008)

Challenges in the design of cognitive radios1. - Behzad Razavi (CICC, 2009)

A 10b 500MHz 55mW CMOS ADC. - Ashutosh Verma; Behzad Razavi (ISSCC, 2009)

U-PAS: A user-friendly ADC simulator for courses on analog design. - Bibhudatta Sahoo 003; Behzad Razavi (MSE, 2009)

Systematic Transistor and Inductor Modeling for Millimeter-Wave Design. - ChuanKang Liang; Behzad Razavi (IEEE J. Solid State Circuits, 2009)

A New Transceiver Architecture for the 60-GHz Band. - Ali Parsa; Behzad Razavi (IEEE J. Solid State Circuits, 2009)

A 12-Bit 200-MHz CMOS ADC. - Bibhudatta Sahoo 003; Behzad Razavi (IEEE J. Solid State Circuits, 2009)

A 10-Bit 500-MS/s 55-mW CMOS ADC. - Ashutosh Verma; Behzad Razavi (IEEE J. Solid State Circuits, 2009)

Design of Millimeter-Wave CMOS Radios: A Tutorial. - Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

The Role of PLLs in Future Wireline Transmitters. - Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

CMOS phase-locked loops for frequency synthesis. - Ian Galton; Behzad Razavi; John Cowles; Peter R. Kinget (ISSCC, 2010)

A 20Gb/s 40mW equalizer in 90nm CMOS technology. - Sameh A. Ibrahim; Behzad Razavi (ISSCC, 2010)

Cognitive Radio Design Challenges and Techniques. - Behzad Razavi (IEEE J. Solid State Circuits, 2010)

A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators. - Mohamed Aboudina; Behzad Razavi (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Cellular and wireless LAN transceivers: From systems to circuit design. - John R. Long; Hooman Darabi; Frank Op't Eynde; Behzad Razavi; Robert Bogdan Staszewski (ISSCC, 2011)

Low-Power CMOS Equalizer Design for 20-Gb/s Systems. - Sameh A. Ibrahim; Behzad Razavi (IEEE J. Solid State Circuits, 2011)

Transmitter Linearization by Beamforming. - ChuanKang Liang; Behzad Razavi (IEEE J. Solid State Circuits, 2011)

A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology. - Behzad Razavi (IEEE J. Solid State Circuits, 2011)

A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion. - Sedigheh Hashemi; Behzad Razavi (CICC, 2012)

Problem of timing mismatch in interleaved ADCs. - Behzad Razavi (CICC, 2012)

A 25-Gb/s 5-mWCMOS CDR/deserializer. - Jun Won Jung; Behzad Razavi (VLSIC, 2012)

A 10-bit 1-GHz 33-mW CMOS ADC. - Bibhudatta Sahoo 003; Behzad Razavi (VLSIC, 2012)

A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications. - Aliakbar Homayoun; Behzad Razavi (CICC, 2013)

Charge steering: A low-power design paradigm. - Behzad Razavi (CICC, 2013)

A 25-Gb/s 5-mW CMOS CDR/Deserializer. - Jun Won Jung; Behzad Razavi (IEEE J. Solid State Circuits, 2013)

A Harmonic-Rejecting CMOS LNA for Broadband Radios. - Joung Won Park; Behzad Razavi (IEEE J. Solid State Circuits, 2013)

Design Considerations for Interleaved ADCs. - Behzad Razavi (IEEE J. Solid State Circuits, 2013)

A 10-b 1-GHz 33-mW CMOS ADC. - Bibhudatta Sahoo 003; Behzad Razavi (IEEE J. Solid State Circuits, 2013)

Analysis of Phase Noise in Phase/Frequency Detectors. - Aliakbar Homayoun; Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply. - Abishek Manian; Behzad Razavi (CICC, 2014)

Recent developments in RF receivers. - Behzad Razavi (CICC, 2014)

The role of translational circuits in RF receiver design. - Behzad Razavi (CICC, 2014)

2.4 A 25Gb/s 5.8mW CMOS equalizer. - Jun Won Jung; Behzad Razavi (ISSCC, 2014)

20.8 A 20mW GSM/WCDMA receiver with RF channel selection. - Joung Won Park; Behzad Razavi (ISSCC, 2014)

A receiver architecture for intra-band carrier aggregation. - Sy-Chyuan Hwu; Behzad Razavi (VLSIC, 2014)

A 10-Bit 800-MHz 19-mW CMOS ADC. - Shiuh-Hua Wood Chiang; Hyuk Sun; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

Analysis of Metastability in Pipelined ADCs. - Sedigheh Hashemi; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate. - Sedigheh Hashemi; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise. - Aliakbar Homayoun; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

Channel Selection at RF Using Miller Bandpass Filters. - Joung Won Park; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

An 8 Bit 4 GS/s 120 mW CMOS ADC. - Hegong Wei; Peng Zhang; Bibhudatta Sahoo 003; Behzad Razavi (IEEE J. Solid State Circuits, 2014)

The future of radios. - Behzad Razavi (ISCAS, 2015)

25.7 A 2.4GHz 4mW inductorless RF synthesizer. - Long Kong; Behzad Razavi (ISSCC, 2015)

A 40-Gb/s 9.2-mW CMOS equalizer. - Abishek Manian; Behzad Razavi (VLSIC, 2015)

A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply. - Joseph Palackal Mathew; Long Kong; Behzad Razavi (VLSIC, 2015)

A Low-Power CMOS Receiver for 5 GHz WLAN. - Aliakbar Homayoun; Behzad Razavi (IEEE J. Solid State Circuits, 2015)

An RF Receiver for Intra-Band Carrier Aggregation. - Sy-Chyuan Hwu; Behzad Razavi (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s 5.8 mW CMOS Equalizer. - Jun Won Jung; Behzad Razavi (IEEE J. Solid State Circuits, 2015)

23.8 A 40Gb/s 14mW CMOS wireline receiver. - Abishek Manian; Behzad Razavi (ISSCC, 2016)

A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer. - Long Kong; Behzad Razavi (IEEE J. Solid State Circuits, 2016)

On the Stability of Charge-Pump Phase-Locked Loops. - Aliakbar Homayoun; Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW. - Long Kong; Behzad Razavi (ISSCC, 2017)

A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer. - Long Kong; Behzad Razavi (IEEE J. Solid State Circuits, 2017)

Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. - John R. Long; Jan Craninckx; Behzad Razavi (IEEE J. Solid State Circuits, 2017)

A 40-Gb/s 14-mW CMOS Wireline Receiver. - Abishek Manian; Behzad Razavi (IEEE J. Solid State Circuits, 2017)

Analysis of Second-Order Intermodulation in Miller Bandpass Filters. - Joung Won Park; Behzad Razavi (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 32-mW 40-Gb/s CMOS NRZ transmitter. - Yikun Chang; Abishek Manian; Long Kong; Behzad Razavi (CICC, 2018)

An Alternative Analysis of Noise Folding in Fractional-N Synthesizers. - Behzad Razavi (ISCAS, 2018)

A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance. - Long Kong; Yikun Chang; Behzad Razavi (VLSI Circuits, 2018)

An 80-Gb/s 44-mW Wireline PAM4 Transmitter. - Yikun Chang; Abishek Manian; Long Kong; Behzad Razavi (IEEE J. Solid State Circuits, 2018)

A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25fREF. - Long Kong; Behzad Razavi (IEEE J. Solid State Circuits, 2018)

A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax. - Fei Song; Yu Zhao; Bart Wu; Litian Tang; Leon Lin; Behzad Razavi (ISSCC, 2019)

An Inductorless 20-Gb/s CDR With High Jitter Tolerance. - Long Kong; Yikun Chang; Behzad Razavi (IEEE J. Solid State Circuits, 2019)

Instrument Design and Performance of the High-Frequency Airborne Microwave and Millimeter-Wave Radiometer. - Xavier Bosch-Lluis; Victoria D. Hadel; Thaddeus P. Johnson; Mehmet Ogut; James Ranson; Steven C. Reising; Pekka Kangaslahti; Alan B. Tanner; Shannon T. Brown; Sharmila Padmanabhan; Chaitali Parashare; Oliver Montes; et al. (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019)

Lower Bounds on Power Consumption of Clock Generators for ADCs. - Behzad Razavi (ISCAS, 2020)

A Digital RF Transmitter With Background Nonlinearity Correction. - Seyed Mehrdad Babamir; Behzad Razavi (IEEE J. Solid State Circuits, 2020)

Low-Power Techniques for Wireline Systems. - Behzad Razavi (ESSCIRC, 2021)

11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS. - Atharav Atharav; Behzad Razavi (ISSCC, 2021)

A 0.4-6 GHz Receiver for LTE and WiFi. - Hossein Razavi; Behzad Razavi (VLSI Circuits, 2021)

A 27-73 GHz Injection-Locked Frequency Divider. - Hossein Razavi; Behzad Razavi (VLSI Circuits, 2021)

A 19-GHz PLL with 20.3-fs Jitter. - Yu Zhao; Behzad Razavi (VLSI Circuits, 2021)

Jitter-Power Trade-Offs in PLLs. - Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Circuit Bandwidth Requirements for NRZ and PAM4 Signals. - Mahdi Forghani; Behzad Razavi (ISCAS, 2022)

Optimal Distribution of High-Speed Clocks on Transceiver Chips. - Makar Chand Snai; Behzad Razavi (ISCAS, 2022)

Phase Noise Integration Limits for Jitter Calculation. - Yu Zhao; Behzad Razavi (ISCAS, 2022)

A 300GHz 52mW CMOS Receiver with On-Chip LO Generation. - Onur Memioglu; Yu Zhao; Behzad Razavi (ISSCC, 2022)

A 56GHz 23mW Fractional-N PLL with 110fs Jitter. - Yu Zhao; Onur Memioglu; Behzad Razavi (ISSCC, 2022)

A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS. - Atharav Atharav; Behzad Razavi (IEEE J. Solid State Circuits, 2022)

A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. - Guanrong Hou; Behzad Razavi (IEEE J. Solid State Circuits, 2022)

A 0.4-6 GHz Receiver for Cellular and WiFi Applications. - Hossein Razavi; Behzad Razavi (IEEE J. Solid State Circuits, 2022)

Relation Between INL and ACPR of RF DACs. - Seyed Mehrdad Babamir; Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply. - Matias Jara; Behzad Razavi (CICC, 2023)

A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis. - Pawan K. Khanna; Yu Zhao; Mahdi Forghani; Behzad Razavi (ESSCIRC, 2023)

A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology. - Mahdi Forghani; Yu Zhao; Pawan K. Khanna; Behzad Razavi (VLSI Technology and Circuits, 2023)

A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation. - Onur Memioglu; Yu Zhao; Behzad Razavi (IEEE J. Solid State Circuits, 2023)

A Study of Injection Locking in Oscillators and Frequency Dividers. - Hossein Razavi; Behzad Razavi (IEEE J. Solid State Circuits, 2023)

A 20-GHz PLL With 20.9-fs Random Jitter. - Yu Zhao; Mahdi Forghani; Behzad Razavi (IEEE J. Solid State Circuits, 2023)

A 56-GHz Fractional-N PLL With 110-fs Jitter. - Yu Zhao; Onur Memioglu; Long Kong; Behzad Razavi (IEEE J. Solid State Circuits, 2023)

Performance Bounds of ADC-Based Receivers Due to Clock Jitter. - Kshitiz Tyagi; Behzad Razavi (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2. - Kshitiz Tyagi; Behzad Razavi (VLSI Technology and Circuits, 2024)

A Predictive SAR ADC Architecture. - Matias Jara; Behzad Razavi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)