Bei Yu

CoRR, 2024

Classes Are Not Equal: An Empirical Study on Image Recognition Fairness.

[BibT_eX]

[DOI]

CoRR, 2024

SoLA: Solver-Layer Adaption of LLM for Better Logic Reasoning.

[BibT_eX]

[DOI]

CoRR, 2024

BetterV: Controlled Verilog Generation with Discriminative Guidance.

[BibT_eX]

[DOI]

CoRR, 2024

Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks.

[BibT_eX]

[DOI]

Haoyuan Wu

Haisheng Zheng

CoRR, 2024

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

FuILT: Full Chip ILT System With Boundary Healing.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

IncreMacro: Incremental Macro Placement Refinement.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Large Language Models for EDA: Future or Mirage?

[BibT_eX]

[DOI]

Zhuolun He

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 2024 International Symposium on Physical Design, 2024

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Progressively Knowledge Distillation via Re-parameterizing Diffusion Reverse Process.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

Aging-Aware Critical Path Selection via Graph Attention Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

DevelSet: Deep Neural Level Set for Instant Mask Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Conditional Temporal Variational AutoEncoder for Action Video Prediction.

[BibT_eX]

[DOI]

Int. J. Comput. Vis., October, 2023

DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

DSGN++: Exploiting Visual-Spatial Relation for Stereo-Based 3D Detectors.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., April, 2023

A GPU-Enabled Level-Set Method for Mask Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

Machine Learning in Advanced IC Design: A Methodological Survey.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

IEEE Trans Autom. Sci. Eng., 2023

Adaptive Perspective Distillation for Semantic Segmentation.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2023

SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design.

[BibT_eX]

[DOI]

CoRR, 2023

TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices.

[BibT_eX]

[DOI]

CoRR, 2023

On the Evaluation of Generative Models in Distributed Learning Tasks.

[BibT_eX]

[DOI]

CoRR, 2023

Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration.

[BibT_eX]

[DOI]

CoRR, 2023

Floorplet: Performance-aware Floorplan Framework for Chiplet Integration.

[BibT_eX]

[DOI]

CoRR, 2023

Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2023

Decoupled Kullback-Leibler Divergence Loss.

[BibT_eX]

[DOI]

CoRR, 2023

Towards Versatile and Efficient Visual Knowledge Injection into Pre-trained Language Models with Cross-Modal Adapters.

[BibT_eX]

[DOI]

CoRR, 2023

GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition.

[BibT_eX]

[DOI]

Guojin Chen

CoRR, 2023

LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Machine Learning in EDA: When and How.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU.

[BibT_eX]

[DOI]

Proceedings of the 52nd International Conference on Parallel Processing, 2023

Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2023

Efficient Deep Space Filling Curve.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Heterogeneous Acceleration for Design Rule Checking.

[BibT_eX]

[DOI]

Zhuolun He

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ATFormer: A Learned Performance Model with Transfer Learning Across Devices for Deep Learning Tensor Programs.

[BibT_eX]

[DOI]

Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023

Efficient Design Rule Checking with GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Fast and Accurate Wire Timing Estimation Based on Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Mitigating Distribution Shift for Congestion Optimization in Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

DiffPattern: Layout Pattern Generation via Discrete Diffusion.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Restructure-Tolerant Timing Prediction via Multimodal Fusion.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Efficient ILT via Multi-level Lithography Simulation.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Layout Decomposition via Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

On a Moreau Envelope Wirelength Model for Analytical Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.

[BibT_eX]

[DOI]

Jianwang Zhai

Yici Cai

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Mixed-Type Wafer Failure Pattern Recognition.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper).

[BibT_eX]

[DOI]

Su Zheng

Martin D. F. Wong

Proceedings of the 15th IEEE International Conference on ASIC, 2023

AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

Efficient Layout Hotspot Detection via Neural Architecture Search.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

An Efficient Sharing Grouped Convolution via Bayesian Learning.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2022

Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Counteracting Adversarial Attacks in Autonomous Driving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Adaptive Layout Decomposition With Graph Embedding Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Pin-Accessible Legalization for Mixed-Cell-Height Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Hotspot Detection via Attention-Based Deep Layout Metric Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

High-Speed Adder Design Space Exploration via Graph Neural Processes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Faster Region-Based Hotspot Detection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DAMO: Deep Agile Mask Optimization for Full-Chip Scale.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Enabling Data Movement and Computation Pipelining in Deep Learning Compiler.

[BibT_eX]

[DOI]

CoRR, 2022

Generalized Parametric Contrastive Learning.

[BibT_eX]

[DOI]

CoRR, 2022

Rethinking Graph Neural Networks for the Graph Coloring Problem.

[BibT_eX]

[DOI]

CoRR, 2022

PVDD: A Practical Video Denoising Dataset with Real-World Dynamic Scenes.

[BibT_eX]

[DOI]

CoRR, 2022

Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Multi-Package Co-Design for Chiplet Integration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms.

[BibT_eX]

[DOI]

Zhuolun He

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Efficient Point Cloud Analysis Using Hilbert Curve.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2022, 2022

TRADER: A Practical Track-Assignment-Based Detailed Router.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Efficient Hotspot Detection via Graph Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Functionality matters in netlist representation learning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

GTuner: tuning DNN computations on GPU via graph attention network.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

PCL: Proxy-based Contrastive Learning for Domain Generalization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Context-Based Contrastive Learning for Scene Text Recognition.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

Machine Learning for Electronic Design Automation: A Survey.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenMPL: An Open-Source Layout Decomposer.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DAC-SDC Low Power Object Detection Challenge for UAV Applications.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2021

VLSI mask optimization: From shallow to deep learning.

[BibT_eX]

[DOI]

Integr., 2021

Routing Towards Discriminative Power of Class Capsules.

[BibT_eX]

[DOI]

Shuhe Li

CoRR, 2021

Learning Point Clouds in EDA.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Seeing Dynamic Scene in the Dark: A High-Quality Video Dataset with Mechatronic Alignment.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Parametric Contrastive Learning.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Hotspot Detection via Multi-task Learning and Transformer Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Graph Learning-Based Arithmetic Block Identification.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Global Placement with Deep Learning-Enabled Explicit Routability Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards AQFP-Capable Physical Design Automation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Physical Synthesis for Advanced Neural Network Processors.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper).

[BibT_eX]

[DOI]

Tinghuan Chen

Qi Sun

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection.

[BibT_eX]

[DOI]

Ramesh Karri

Siddharth Garg

ACM Trans. Design Autom. Electr. Syst., 2020

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SRAF Insertion via Supervised Dictionary Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Fault tolerance in memristive crossbar-based neuromorphic computing systems.

[BibT_eX]

[DOI]

Integr., 2020

DSA guiding template assignment with multiple redundant via and dummy via insertion.

[BibT_eX]

[DOI]

Integr., 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).

[BibT_eX]

[DOI]

CoRR, 2020

Understanding Graphs in EDA: From Shallow to Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DeepBillboard: systematic physical-world testing of autonomous driving systems.

[BibT_eX]

[DOI]

Proceedings of the ICSE '20: 42nd International Conference on Software Engineering, Seoul, South Korea, 27 June, 2020

Learn to Floorplan through Acquisition of Effective Local Search Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Hotspot Detection via Attention-based Deep Layout Metric Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DAMO: Deep Agile Mask Optimization for Full Chip Scale.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Tensor Low-Rank Reconstruction for Semantic Segmentation.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

Dive Deeper into Box for Object Detection.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

Adaptive Layout Decomposition with Graph Embedding Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

[BibT_eX]

[DOI]

Derong Liu

Vinicius S. Livramento

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Provably Secure Camouflaging Strategy for IC Protection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Adaptive 3D-IC TSV Fault Tolerance Structure Generation.

[BibT_eX]

[DOI]

Song Chen

Qi Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Recent advances in convolutional neural network acceleration.

[BibT_eX]

[DOI]

Neurocomputing, 2019

CAD Tool Design Space Exploration via Bayesian Optimization.

[BibT_eX]

[DOI]

Ziyang Yu

CoRR, 2019

Automatic Layout Generation with Applications in Machine Learning Engine Evaluation.

[BibT_eX]

[DOI]

CoRR, 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.

[BibT_eX]

[DOI]

Ramesh Karri

Siddharth Garg

CoRR, 2019

A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Tools with Artificial Intelligence, 2019

Power-Driven DNN Dataflow Optimization on FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.

[BibT_eX]

[DOI]

Karthikeyan Natarajan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.

[BibT_eX]

[DOI]

Ozgur Sinanoglu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FIT: Fill Insertion Considering Timing.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient Layout Hotspot Detection via Binarized Residual Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Faster Region-based Hotspot Detection.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Sensor Drift Calibration via Spatial Correlation Model in Smart Building.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Hardware-software co-design of slimmed optical neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Detecting multi-layer layout hotspots with adaptive squish patterns.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A local optimal method on DSA guiding template assignment with redundant/dummy via insertion.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

SRAF insertion via supervised dictionary learning.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

IEEE Transactions on Sustainable Computing: Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems.

[BibT_eX]

[DOI]

Shiyan Hu

Huafeng Yu

IEEE Trans. Sustain. Comput., 2018

SD-PUF: Spliced Digital Physical Unclonable Function.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

[BibT_eX]

[DOI]

Natarajan Viswanathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.

[BibT_eX]

[DOI]

Jian Kuang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems.

[BibT_eX]

[DOI]

CoRR, 2018

OpenMPL: An Open Source Layout Decomposer.

[BibT_eX]

[DOI]

CoRR, 2018

A Unified Approximation Framework for Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Power Grid Reduction by Sparse Convex Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

GAN-OPC: mask optimization with lithography-guided generative adversarial nets.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.

[BibT_eX]

[DOI]

Haocheng Li

Wing-Kai Chow

Gengjie Chen

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Incremental Layer Assignment for Timing Optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Incremental Layer Assignment Driven by an External Signoff Timing Engine.

[BibT_eX]

[DOI]

Vinicius S. Livramento

José Luís Almada Güntzel

Luiz C. V. dos Santos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.

[BibT_eX]

[DOI]

Yibo Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Special Issue on Scalable Cyber-Physical Systems.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

Stitch aware detailed placement for multiple E-beam lithography.

[BibT_eX]

[DOI]

Integr., 2017

Smart building uncertainty analysis via adaptive Lasso.

[BibT_eX]

[DOI]

Bingqing Lin

IET Cyper-Phys. Syst.: Theory & Appl., 2017

Methodologies for layout decomposition and mask optimization: A systematic review.

[BibT_eX]

[DOI]

Xuan Zeng

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Accelerating chip design with machine learning: From pre-silicon to post-silicon.

[BibT_eX]

[DOI]

Cheng Zhuo

Di Gao

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

F1B: Algorithms, models and simulation for systems.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Lithography hotspot detection: From shallow to deep learning.

[BibT_eX]

[DOI]

Yajun Lin

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Bilinear Lithography Hotspot Detection.

[BibT_eX]

[DOI]

Hang Zhang

Fengyuan Zhu

Haocheng Li

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

[BibT_eX]

[DOI]

Chak-Wa Pui

Gengjie Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A unified framework for simultaneous layout decomposition and mask optimization.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A utility-driven data transmission optimization strategy in large scale cyber-physical systems.

[BibT_eX]

[DOI]

Soumi Chattopadhyay

Ansuman Banerjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Layout Decomposition for Triple Patterning.

[BibT_eX]

[DOI]

Encyclopedia of Algorithms, 2016

EBL Overlapping Aware Stencil Planning for MCC System.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Design for manufacturability and reliability in extreme-scaling VLSI.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography.

[BibT_eX]

[DOI]

Jiaojiao Ou

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization.

[BibT_eX]

[DOI]

Hang Zhang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

LRR-DPUF: learning resilient and reliable digital physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incorporating cut redistribution with mask assignment to enable 1D gridded design.

[BibT_eX]

[DOI]

Jian Kuang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Incremental layer assignment for critical path timing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.

[BibT_eX]

[DOI]

Tetsuaki Matsunawa

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

VLSI layout hotspot detection based on discriminative feature extraction.

[BibT_eX]

[DOI]

Hang Zhang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Layout Decomposition for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

TILA: Timing-Driven Incremental Layer Assignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Pushing multiple patterning in sub-10nm: are we ready?

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Machine learning and pattern matching in physical design.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Electromigration-aware redundant via insertion.

[BibT_eX]

[DOI]

Jiwoo Pak

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).

[BibT_eX]

[DOI]

CoRR, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.

[BibT_eX]

[DOI]

CoRR, 2014

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.

[BibT_eX]

[DOI]

Sheqin Dong

Satoshi Goto

CoRR, 2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI.

[BibT_eX]

[DOI]

CoRR, 2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.

[BibT_eX]

[DOI]

CoRR, 2014

Layout Decomposition for Quadruple Patterning Lithography and Beyond.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Self-aligned double patterning layout decomposition with complementary e-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Design for Manufacturing With Emerging Nanolithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Methodology for standard cell compliance and detailed placement for triple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A high-performance triple patterning layout decomposer with balanced density.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

L-shape based layout fracturing for e-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lithography hotspot detection and mitigation in nanometer VLSI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.

[BibT_eX]

[DOI]

Kun Yuan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

VLSI CAD for emerging nanolithography.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TRIAD: A triple patterning lithography aware detailed router.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.

[BibT_eX]

[DOI]

Duo Ding