Bei Yu

According to our database1, Bei Yu authored at least 116 papers between 2009 and 2020.

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2020
Fault tolerance in memristive crossbar-based neuromorphic computing systems.
Integration, 2020

DSA guiding template assignment with multiple redundant via and dummy via insertion.
Integration, 2020

2019
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Provably Secure Camouflaging Strategy for IC Protection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Adaptive 3D-IC TSV Fault Tolerance Structure Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Recent advances in convolutional neural network acceleration.
Neurocomputing, 2019

VLSI Mask Optimization: From Shallow To Deep Learning.
CoRR, 2019

CAD Tool Design Space Exploration via Bayesian Optimization.
CoRR, 2019

Automatic Layout Generation with Applications in Machine Learning Engine Evaluation.
CoRR, 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.
CoRR, 2019

Power-Driven DNN Dataflow Optimization on FPGA.
Proceedings of the International Conference on Computer-Aided Design, 2019

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FIT: Fill Insertion Considering Timing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient Layout Hotspot Detection via Binarized Residual Neural Network.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Faster Region-based Hotspot Detection.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Sensor Drift Calibration via Spatial Correlation Model in Smart Building.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Hardware-software co-design of slimmed optical neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Detecting multi-layer layout hotspots with adaptive squish patterns.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A local optimal method on DSA guiding template assignment with redundant/dummy via insertion.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

SRAF insertion via supervised dictionary learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP.
IEEE Trans. VLSI Syst., 2018

IEEE Transactions on Sustainable Computing: Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems.
T-SUSC, 2018

SD-PUF: Spliced Digital Physical Unclonable Function.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems.
CoRR, 2018

OpenMPL: An Open Source Layout Decomposer.
CoRR, 2018

DAC-SDC Low Power Object Detection Challenge for UAV Applications.
CoRR, 2018

A Unified Approximation Framework for Deep Neural Networks.
CoRR, 2018

Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning.
CoRR, 2018

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Power Grid Reduction by Sparse Convex Optimization.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

GAN-OPC: mask optimization with lithography-guided generative adversarial nets.
Proceedings of the 55th Annual Design Automation Conference, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Incremental Layer Assignment for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2017

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Incremental Layer Assignment Driven by an External Signoff Timing Engine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Special Issue on Scalable Cyber-Physical Systems.
J. Parallel Distrib. Comput., 2017

Stitch aware detailed placement for multiple E-beam lithography.
Integration, 2017

Smart building uncertainty analysis via adaptive Lasso.
IET Cyper-Phys. Syst.: Theory & Appl., 2017

Methodologies for layout decomposition and mask optimization: A systematic review.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Accelerating chip design with machine learning: From pre-silicon to post-silicon.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Lithography hotspot detection: From shallow to deep learning.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Bilinear Lithography Hotspot Detection.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A unified framework for simultaneous layout decomposition and mask optimization.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A utility-driven data transmission optimization strategy in large scale cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning.
Proceedings of the 54th Annual Design Automation Conference, 2017

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Layout Decomposition for Triple Patterning.
Encyclopedia of Algorithms, 2016

EBL Overlapping Aware Stencil Planning for MCC System.
ACM Trans. Design Autom. Electr. Syst., 2016

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.
ACM Trans. Design Autom. Electr. Syst., 2016

Design for manufacturability and reliability in extreme-scaling VLSI.
SCIENCE CHINA Information Sciences, 2016

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

LRR-DPUF: learning resilient and reliable digital physical unclonable function.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incorporating cut redistribution with mask assignment to enable 1D gridded design.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Incremental layer assignment for critical path timing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

VLSI layout hotspot detection based on discriminative feature extraction.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Layout Decomposition for Triple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

TILA: Timing-Driven Incremental Layer Assignment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Pushing multiple patterning in sub-10nm: are we ready?
Proceedings of the 52nd Annual Design Automation Conference, 2015

Machine learning and pattern matching in physical design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Electromigration-aware redundant via insertion.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).
CoRR, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.
CoRR, 2014

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.
CoRR, 2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI.
CoRR, 2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.
CoRR, 2014

Layout Decomposition for Quadruple Patterning Lithography and Beyond.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Self-aligned double patterning layout decomposition with complementary e-beam lithography.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Design for Manufacturing With Emerging Nanolithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Methodology for standard cell compliance and detailed placement for triple patterning lithography.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A high-performance triple patterning layout decomposer with balanced density.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

L-shape based layout fracturing for e-beam lithography.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lithography hotspot detection and mitigation in nanometer VLSI.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.
IEICE Transactions, 2012

VLSI CAD for emerging nanolithography.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TRIAD: A triple patterning lithography aware detailed router.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Layout decomposition for triple patterning lithography.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A revisit to voltage partitioning problem.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Floorplanning and topology generation for application-specific network-on-chip.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Voltage and Level-Shifter Assignment Driven Floorplanning.
IEICE Transactions, 2009

Voltage-island driven floorplanning considering level-shifter positions.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009


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