Voltage-island driven floorplanning considering level-shifter positions. - Bei Yu 001; Sheqin Dong; Satoshi Goto; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2009)

Voltage and Level-Shifter Assignment Driven Floorplanning. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Floorplanning and topology generation for application-specific network-on-chip. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (ASP-DAC, 2010)

A revisit to voltage partitioning problem. - Tao Lin; Sheqin Dong; Bei Yu 001; Song Chen 001; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2010)

Network flow-based simultaneous retiming and slack budgeting for low power design. - Bei Yu 001; Sheqin Dong; Yuchun Ma; Tao Lin; Yu Wang 002; Song Chen 001; Satoshi Goto (ASP-DAC, 2011)

Layout decomposition for triple patterning lithography. - Bei Yu 001; Kun Yuan 002; Boyang Zhang; Duo Ding; David Z. Pan (ICCAD, 2011)

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. - Wei Zhong; Bei Yu 001; Song Chen 001; Takeshi Yoshimura; Sheqin Dong; Satoshi Goto (ISQED, 2011)

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. - Duo Ding; Bei Yu 001; Joydeep Ghosh; David Z. Pan (ASP-DAC, 2012)

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. - Duo Ding; Bei Yu 001; David Z. Pan (ASP-DAC, 2012)

TRIAD: A triple patterning lithography aware detailed router. - Yen-Hung Lin; Bei Yu 001; David Z. Pan; Yih-Lang Li (ICCAD, 2012)

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). - Bei Yu 001; Jhih-Rong Gao; Duo Ding; Yongchan Ban; Jae-Seok Yang; Kun Yuan 002; Minsik Cho; David Z. Pan (ICCAD, 2012)

VLSI CAD for emerging nanolithography. - David Z. Pan; Jhih-Rong Gao; Bei Yu 001 (VLSI-DAT, 2012)

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. - Wei Zhong; Takeshi Yoshimura; Bei Yu 001; Song Chen 001; Sheqin Dong; Satoshi Goto (IEICE Trans. Electron., 2012)

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. - Kun Yuan 002; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Lithography hotspot detection and mitigation in nanometer VLSI. - Jhih-Rong Gao; Bei Yu 001; Duo Ding; David Z. Pan (ASICON, 2013)

L-shape based layout fracturing for e-beam lithography. - Bei Yu 001; Jhih-Rong Gao; David Z. Pan (ASP-DAC, 2013)

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. - Bei Yu 001; Kun Yuan 002; Jhih-Rong Gao; David Z. Pan (DAC, 2013)

A high-performance triple patterning layout decomposer with balanced density. - Bei Yu 001; Yen-Hung Lin; Gerard Luk-Pat; Duo Ding; Kevin Lucas; David Z. Pan (ICCAD, 2013)

Methodology for standard cell compliance and detailed placement for triple patterning lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; David Z. Pan (ICCAD, 2013)

Design for Manufacturing With Emerging Nanolithography. - David Z. Pan; Bei Yu 001; Jhih-Rong Gao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Self-aligned double patterning layout decomposition with complementary e-beam lithography. - Jhih-Rong Gao; Bei Yu 001; David Z. Pan (ASP-DAC, 2014)

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. - Jhih-Rong Gao; Xiaoqing Xu; Bei Yu 001; David Z. Pan (DAC, 2014)

Layout Decomposition for Quadruple Patterning Lithography and Beyond. - Bei Yu 001; David Z. Pan (DAC, 2014)

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. - Jhih-Rong Gao; Bei Yu 001; Ru Huang 001; David Z. Pan (CoRR, 2014)

Lithography Hotspot Detection and Mitigation in Nanometer VLSI. - Jhih-Rong Gao; Bei Yu 001; David Z. Pan (CoRR, 2014)

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. - Bei Yu 001; Sheqin Dong; Satoshi Goto (CoRR, 2014)

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting. - Bei Yu 001; Jhih-Rong Gao; David Z. Pan (CoRR, 2014)

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). - Bei Yu 001; Subhendu Roy; Jhih-Rong Gao; David Z. Pan (CoRR, 2014)

Electromigration-aware redundant via insertion. - Jiwoo Pak; Bei Yu 001; David Z. Pan (ASP-DAC, 2015)

Machine learning and pattern matching in physical design. - Bei Yu 001; David Z. Pan; Tetsuaki Matsunawa; Xuan Zeng 001 (ASP-DAC, 2015)

Pushing multiple patterning in sub-10nm: are we ready? - David Z. Pan; Lars Liebmann; Bei Yu 001; Xiaoqing Xu; Yibo Lin (DAC, 2015)

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. - Jiaojiao Ou; Bei Yu 001; Jhih-Rong Gao; David Z. Pan; Moshe Preil; Azat Latypov (ACM Great Lakes Symposium on VLSI, 2015)

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. - Wei Ye 008; Bei Yu 001; David Z. Pan; Yongchan Ban; Lars Liebmann (ACM Great Lakes Symposium on VLSI, 2015)

TILA: Timing-Driven Incremental Layer Assignment. - Bei Yu 001; Derong Liu 002; Salim Chowdhury; David Z. Pan (ICCAD, 2015)

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. - Xiaoqing Xu; Brian Cline; Greg Yeric; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Yibo Lin; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Layout Decomposition for Triple Patterning Lithography. - Bei Yu 001; Kun Yuan 002; Duo Ding; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

VLSI layout hotspot detection based on discriminative feature extraction. - Hang Zhang 010; Haoyu Yang; Bei Yu 001; Evangeline F. Y. Young (APCCAS, 2016)

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC. - Tetsuaki Matsunawa; Bei Yu 001; David Z. Pan (ASP-DAC, 2016)

Incremental layer assignment for critical path timing. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (DAC, 2016)

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ACM Great Lakes Symposium on VLSI, 2016)

Incorporating cut redistribution with mask assignment to enable 1D gridded design. - Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2016)

LRR-DPUF: learning resilient and reliable digital physical unclonable function. - Jin Miao; Meng Li 004; Subhendu Roy; Bei Yu 001 (ICCAD, 2016)

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. - Chak-Wa Pui; Gengjie Chen; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Peishan Tu; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2016)

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. - Hang Zhang 010; Bei Yu 001; Evangeline F. Y. Young (ICCAD, 2016)

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography. - Jiaojiao Ou; Bei Yu 001; David Z. Pan (ISPD, 2016)

Design for manufacturability and reliability in extreme-scaling VLSI. - Bei Yu 001; Xiaoqing Xu; Subhendu Roy; Yibo Lin; Jiaojiao Ou; David Z. Pan (Sci. China Inf. Sci., 2016)

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. - Xiaoqing Xu; Bei Yu 001; Jhih-Rong Gao; Che-Lun Hsu; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2016)

EBL Overlapping Aware Stencil Planning for MCC System. - Bei Yu 001; Kun Yuan 002; Jhih-Rong Gao; Shiyan Hu 001; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2016)

Layout Decomposition for Triple Patterning. - Bei Yu 001; David Z. Pan (Encyclopedia of Algorithms, 2016)

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. - Gengjie Chen; Jian Kuang 001; Zhiliang Zeng; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2017)

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. - Haoyu Yang; Jing Su; Yi Zou; Bei Yu 001; Evangeline F. Y. Young (DAC, 2017)

A utility-driven data transmission optimization strategy in large scale cyber-physical systems. - Soumi Chattopadhyay; Ansuman Banerjee; Bei Yu 001 (DATE, 2017)

A unified framework for simultaneous layout decomposition and mask optimization. - Yuzhe Ma; Jhih-Rong Gao; Jian Kuang 001; Jin Miao; Bei Yu 001 (ICCAD, 2017)

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). - Chak-Wa Pui; Gengjie Chen; Yuzhe Ma; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2017)

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. - Subhendu Roy; Yuzhe Ma; Jin Miao; Bei Yu 001 (ISLPED, 2017)

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. - Jiaojiao Ou; Bei Yu 001; Xiaoqing Xu; Joydeep Mitra; Yibo Lin; David Z. Pan (ISPD, 2017)

Bilinear Lithography Hotspot Detection. - Hang Zhang 010; Fengyuan Zhu; Haocheng Li; Evangeline F. Y. Young; Bei Yu 001 (ISPD, 2017)

Lithography hotspot detection: From shallow to deep learning. - Haoyu Yang; Yajun Lin; Bei Yu 001; Evangeline F. Y. Young (SoCC, 2017)

F1B: Algorithms, models and simulation for systems. - Bei Yu 001 (SoCC, 2017)

Accelerating chip design with machine learning: From pre-silicon to post-silicon. - Cheng Zhuo; Bei Yu 001; Di Gao (SoCC, 2017)

Methodologies for layout decomposition and mask optimization: A systematic review. - Yuzhe Ma; Xuan Zeng 001; Bei Yu 001 (VLSI-SoC, 2017)

Smart building uncertainty analysis via adaptive Lasso. - Bingqing Lin; Bei Yu 001 (IET Cyper-Phys. Syst.: Theory & Appl., 2017)

Stitch aware detailed placement for multiple E-beam lithography. - Yibo Lin; Bei Yu 001; Yi Zou; Zhuo Li 001; Charles J. Alpert; David Z. Pan (Integr., 2017)

Special Issue on Scalable Cyber-Physical Systems. - Meikang Qiu; Saurabh Kumar Garg 001; Rajkumar Buyya; Bei Yu 001; Shiyan Hu 001 (J. Parallel Distributed Comput., 2017)

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. - Yibo Lin; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. - Yibo Lin; Bei Yu 001; Biying Xu; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Incremental Layer Assignment Driven by an External Signoff Timing Engine. - Vinicius S. Livramento; Derong Liu 002; Salim Chowdhury; Bei Yu 001; Xiaoqing Xu; David Z. Pan; José Luís Almada Güntzel; Luiz C. V. dos Santos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits. - Qi Xu; Song Chen 001; Xiaodong Xu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Incremental Layer Assignment for Timing Optimization. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2017)

Routability-driven and fence-aware legalization for mixed-cell-height circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2018)

GAN-OPC: mask optimization with lithography-guided generative adversarial nets. - Haoyu Yang; Shuhe Li; Yuzhe Ma; Bei Yu 001; Evangeline F. Y. Young (DAC, 2018)

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. - Grace Li Zhang; Bing Li 005; Bei Yu 001; David Z. Pan; Ulf Schlichtmann (DATE, 2018)

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. - Qi Xu; Song Chen 001; Bei Yu 001; Feng Wu 001 (ACM Great Lakes Symposium on VLSI, 2018)

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. - Fengxian Jiao; Sheqin Dong; Bei Yu 001; Bing Li 005; Ulf Schlichtmann (ISCAS, 2018)

Power Grid Reduction by Sparse Convex Optimization. - Wei Ye 008; Meng Li 004; Kai Zhong; Bei Yu 001; David Z. Pan (ISPD, 2018)

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach. - Hao Geng; Haoyu Yang; Bei Yu 001; Xingquan Li; Xuan Zeng 001 (ISVLSI, 2018)

A Unified Approximation Framework for Deep Neural Networks. - Yuzhe Ma; Ran Chen 001; Wei Li 159; Fanhua Shang; Wenjian Yu; Minsik Cho; Bei Yu 001 (CoRR, 2018)

OpenMPL: An Open Source Layout Decomposer. - Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (CoRR, 2018)

DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems. - Husheng Zhou; Wei Li 159; Yuankun Zhu; Yuqun Zhang; Bei Yu 001; Lingming Zhang 001; Cong Liu 005 (CoRR, 2018)

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. - Gengjie Chen; Chak-Wa Pui; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. - Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. - Yibo Lin; Bei Yu 001; Meng Li 004; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. - Derong Liu 002; Bei Yu 001; Salim Chowdhury; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

SD-PUF: Spliced Digital Physical Unclonable Function. - Jin Miao; Meng Li 004; Subhendu Roy; Yuzhe Ma; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

IEEE Transactions on Sustainable Computing: Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems. - Shiyan Hu 001; Bei Yu 001; Huafeng Yu (IEEE Trans. Sustain. Comput., 2018)

Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP. - Xingquan Li; Bei Yu 001; Jiaojiao Ou; Jianli Chen; David Z. Pan; Wenxing Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

OpenMPL: An Open Source Layout Decomposer: Invited Paper. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (ASICON, 2019)

SRAF insertion via supervised dictionary learning. - Hao Geng; Haoyu Yang; Yuzhe Ma; Joydeep Mitra; Bei Yu 001 (ASP-DAC, 2019)

A local optimal method on DSA guiding template assignment with redundant/dummy via insertion. - Xingquan Li; Bei Yu 001; Jianli Chen; Wenxing Zhu (ASP-DAC, 2019)

Detecting multi-layer layout hotspots with adaptive squish patterns. - Haoyu Yang; Piyush Pathak; Frank Gennari; Ya-Chieh Lai; Bei Yu 001 (ASP-DAC, 2019)

Hardware-software co-design of slimmed optical neural networks. - Zheng Zhao 003; Derong Liu 002; Meng Li 004; Zhoufeng Ying; Lu Zhang; Biying Xu; Bei Yu 001; Ray T. Chen; David Z. Pan (ASP-DAC, 2019)

Sensor Drift Calibration via Spatial Correlation Model in Smart Building. - Tinghuan Chen; Bingqing Lin; Hao Geng; Bei Yu 001 (DAC, 2019)

Faster Region-based Hotspot Detection. - Ran Chen 001; Wei Zhong; Haoyu Yang; Hao Geng; Xuan Zeng 001; Bei Yu 001 (DAC, 2019)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network. - Yiyang Jiang; Fan Yang 001; Hengliang Zhu; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2019)

FIT: Fill Insertion Considering Timing. - Bentian Jiang; Xiaopeng Zhang 009; Ran Chen 001; Gengjie Chen; Peishan Tu; Wei Li 159; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2019)

Attacking Split Manufacturing from a Deep Learning Perspective. - Haocheng Li; Satwik Patnaik; Abhrajit Sengupta; Haoyu Yang; Johann Knechtel; Bei Yu 001; Evangeline F. Y. Young; Ozgur Sinanoglu (DAC, 2019)

High Performance Graph Convolutional Networks with Applications in Testability Analysis. - Yuzhe Ma; Haoxing Ren; Brucek Khailany; Harbinder Sikka; Lijuan Luo; Karthikeyan Natarajan; Bei Yu 001 (DAC, 2019)

DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder. - Haoyu Yang; Piyush Pathak; Frank Gennari; Ya-Chieh Lai; Bei Yu 001 (DAC, 2019)

Power-Driven DNN Dataflow Optimization on FPGA. - Qi Sun 002; Tinghuan Chen; Jin Miao; Bei Yu 001 (ICCAD, 2019)

A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks. - Yuzhe Ma; Ran Chen 001; Wei Li 159; Fanhua Shang; Wenjian Yu; Minsik Cho; Bei Yu 001 (ICTAI, 2019)

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. - Kang Liu 017; Haoyu Yang; Yuzhe Ma; Benjamin Tan 001; Bei Yu 001; Evangeline F. Y. Young; Ramesh Karri; Siddharth Garg (CoRR, 2019)

Automatic Layout Generation with Applications in Machine Learning Engine Evaluation. - Haoyu Yang; Wen Chen; Piyush Pathak; Frank Gennari; Ya-Chieh Lai; Bei Yu 001 (CoRR, 2019)

CAD Tool Design Space Exploration via Bayesian Optimization. - Yuzhe Ma; Ziyang Yu 001; Bei Yu 001 (CoRR, 2019)

Recent advances in convolutional neural network acceleration. - Qianru Zhang; Meng Zhang 010; Tinghuan Chen; Zhifei Sun; Yuzhe Ma; Bei Yu 001 (Neurocomputing, 2019)

Adaptive 3D-IC TSV Fault Tolerance Structure Generation. - Song Chen 001; Qi Xu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Provably Secure Camouflaging Strategy for IC Protection. - Meng Li 004; Kaveh Shamsi; Travis Meade; Zheng Zhao 003; Bei Yu 001; Yier Jin; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. - Meng Li 004; Bei Yu 001; Yibo Lin; Xiaoqing Xu; Wuxi Li; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. - Derong Liu 002; Bei Yu 001; Vinicius S. Livramento; Salim Chowdhury; Duo Ding; Huy Vo; Akshay Sharma; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. - Yuzhe Ma; Subhendu Roy; Jin Miao; Jiamin Chen; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. - Haoyu Yang; Jing Su; Yi Zou; Yuzhe Ma; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Adaptive Layout Decomposition with Graph Embedding Neural Networks. - Wei Li 159; Jialu Xia; Yuzhe Ma; Jialu Li; Yibo Lin; Bei Yu 001 (DAC, 2020)

Dive Deeper into Box for Object Detection. - Ran Chen 001; Yong Liu; Mengdan Zhang; Shu Liu 005; Bei Yu 001; Yu-Wing Tai (ECCV (22), 2020)

Tensor Low-Rank Reconstruction for Semantic Segmentation. - Wanli Chen; Xinge Zhu; Ruoqi Sun; Junjun He; Ruiyu Li; Xiaoyong Shen; Bei Yu 001 (ECCV (17), 2020)

DAMO: Deep Agile Mask Optimization for Full Chip Scale. - Guojin Chen; Wanli Chen; Yuzhe Ma; Haoyu Yang; Bei Yu 001 (ICCAD, 2020)

Hotspot Detection via Attention-based Deep Layout Metric Learning. - Hao Geng; Haoyu Yang; Lu Zhang; Jin Miao; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (ICCAD, 2020)

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. - Bentian Jiang; Lixin Liu; Yuzhe Ma; Hang Zhang 010; Bei Yu 001; Evangeline F. Y. Young (ICCAD, 2020)

Learn to Floorplan through Acquisition of Effective Local Search Heuristics. - Zhuolun He; Yuzhe Ma; Lu Zhang; Peiyu Liao; Ngai Wong 001; Bei Yu 001; Martin D. F. Wong (ICCD, 2020)

DeepBillboard: systematic physical-world testing of autonomous driving systems. - Husheng Zhou; Wei Li 159; Zelun Kong; Junfeng Guo; Yuqun Zhang; Bei Yu 001; Lingming Zhang 001; Cong Liu 005 (ICSE, 2020)

Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. - Junpeng Wang 002; Qi Xu; Bo Yuan 006; Song Chen 001; Bei Yu 001; Feng Wu 001 (ISCAS, 2020)

Understanding Graphs in EDA: From Shallow to Deep Learning. - Yuzhe Ma; Zhuolun He; Wei Li 159; Lu Zhang; Bei Yu 001 (ISPD, 2020)

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (CoRR, 2020)

DSA guiding template assignment with multiple redundant via and dummy via insertion. - Xingquan Li; Bei Yu 001; Jianli Chen; Wenxing Zhu (Integr., 2020)

Fault tolerance in memristive crossbar-based neuromorphic computing systems. - Qi Xu; Song Chen 001; Hao Geng; Bo Yuan 006; Bei Yu 001; Feng Wu 001; Zhengfeng Huang (Integr., 2020)

SRAF Insertion via Supervised Dictionary Learning. - Hao Geng; Wei Zhong; Haoyu Yang; Yuzhe Ma; Joydeep Mitra; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization. - Yuzhe Ma; Wei Zhong; Shuxiang Hu; Jhih-Rong Gao; Jian Kuang 001; Jin Miao; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. - Haoyu Yang; Shuhe Li; Zihao Deng; Yuzhe Ma; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. - Kang Liu 017; Haoyu Yang; Yuzhe Ma; Benjamin Tan 001; Bei Yu 001; Evangeline F. Y. Young; Ramesh Karri; Siddharth Garg (ACM Trans. Design Autom. Electr. Syst., 2020)

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. - Qi Xu; Hao Geng; Song Chen 001; Bei Yu 001; Feng Wu 001 (ACM Trans. Design Autom. Electr. Syst., 2020)

Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper). - Tinghuan Chen; Qi Sun 002; Bei Yu 001 (ASICON, 2021)

Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. - Tinghuan Chen; Qi Sun 002; Canhui Zhan; Changze Liu; Huatao Yu; Bei Yu 001 (ASP-DAC, 2021)

Physical Synthesis for Advanced Neural Network Processors. - Zhuolun He; Peiyu Liao; Siting Liu 002; Yuzhe Ma; Yibo Lin; Bei Yu 001 (ASP-DAC, 2021)

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction. - Wei Li 159; Yuxiao Qu; Gengjie Chen; Yuzhe Ma; Bei Yu 001 (ASP-DAC, 2021)

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. - Haoyu Yang; Shifan Zhang; Kang Liu 017; Siting Liu 002; Benjamin Tan 001; Ramesh Karri; Siddharth Garg; Bei Yu 001; Evangeline F. Y. Young (ASP-DAC, 2021)

NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. - Junzhe Cai; Changhao Yan; Yuzhe Ma; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2021)

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration. - Yifeng Xiao; Miaodi Su; Haoyu Yang; Jianli Chen; Jun Yu 010; Bei Yu 001 (DAC, 2021)

Towards AQFP-Capable Physical Design Automation. - Hongjia Li; Mengshu Sun; Tianyun Zhang; Olivia Chen; Nobuyuki Yoshikawa; Bei Yu 001; Yanzhi Wang; Yibo Lin (DATE, 2021)

Global Placement with Deep Learning-Enabled Explicit Routability Optimization. - Siting Liu 002; Qi Sun 002; Peiyu Liao; Yibo Lin; Bei Yu 001 (DATE, 2021)

Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning. - Qi Sun 002; Chen Bai; Hao Geng; Bei Yu 001 (DATE, 2021)

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. - Qi Sun 002; Tinghuan Chen; Siting Liu 002; Jin Miao; Jianli Chen; Hao Yu 001; Bei Yu 001 (DATE, 2021)

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. - Chen Bai; Qi Sun 002; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ICCAD, 2021)

AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU. - Yang Bai; Xufeng Yao; Qi Sun 002; Bei Yu 001 (ICCAD, 2021)

When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. - Hao Geng; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (ICCAD, 2021)

Graph Learning-Based Arithmetic Block Identification. - Zhuolun He; Ziyi Wang 010; Chen Bai; Haoyu Yang; Bei Yu 001 (ICCAD, 2021)

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ICCAD, 2021)

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. - Wenqian Zhao; Qi Sun 002; Yang Bai; Wenbo Li 002; Haisheng Zheng; Bei Yu 001; Martin D. F. Wong (ICCAD, 2021)

Hotspot Detection via Multi-task Learning and Transformer Encoder. - Binwu Zhu; Ran Chen 001; Xinyun Zhang; Fan Yang 001; Xuan Zeng 001; Bei Yu 001; Martin D. F. Wong (ICCAD, 2021)

Parametric Contrastive Learning. - Jiequan Cui; Zhisheng Zhong; Shu Liu 005; Bei Yu 001; Jiaya Jia (ICCV, 2021)

Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning. - Qi Sun 002; Chen Bai; Tinghuan Chen; Hao Geng; Xinyun Zhang; Yang Bai; Bei Yu 001 (ICCV, 2021)

Seeing Dynamic Scene in the Dark: A High-Quality Video Dataset with Mechatronic Alignment. - Ruixing Wang; Xiaogang Xu 002; Chi-Wing Fu; Jiangbo Lu; Bei Yu 001; Jiaya Jia (ICCV, 2021)

Learning Point Clouds in EDA. - Wei Li 159; Guojin Chen; Haoyu Yang; Ran Chen 001; Bei Yu 001 (ISPD, 2021)

Routing Towards Discriminative Power of Class Capsules. - Haoyu Yang; Shuhe Li; Bei Yu 001 (CoRR, 2021)

VLSI mask optimization: From shallow to deep learning. - Haoyu Yang; Wei Zhong; Yuzhe Ma; Hao Geng; Ran Chen 001; Wanli Chen; Bei Yu 001 (Integr., 2021)

DAC-SDC Low Power Object Detection Challenge for UAV Applications. - Xiaowei Xu 004; Xinyi Zhang 001; Bei Yu 001; Xiaobo Sharon Hu; Christopher Rowen; Jingtong Hu; Yiyu Shi 001 (IEEE Trans. Pattern Anal. Mach. Intell., 2021)

Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building. - Tinghuan Chen; Bingqing Lin; Hao Geng; Shiyan Hu 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

OpenMPL: An Open-Source Layout Decomposer. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Lu Zhang; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. - Haocheng Li; Satwik Patnaik; Mohammed Ashraf; Haoyu Yang; Johann Knechtel; Bei Yu 001; Ozgur Sinanoglu; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning. - Haoyu Yang; Shuhe Li; Cyrus Tabery; Bingqing Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Machine Learning for Electronic Design Automation: A Survey. - Guyue Huang; Jingbo Hu; Yifan He 003; Jialong Liu; Mingyuan Ma; Zhaoyang Shen; Juejian Wu; Yuanfan Xu; Hengrui Zhang; Kai Zhong; Xuefei Ning; Yuzhe Ma; et al. (ACM Trans. Design Autom. Electr. Syst., 2021)

Context-Based Contrastive Learning for Scene Text Recognition. - Xinyun Zhang; Binwu Zhu; Xufeng Yao; Qi Sun 002; Ruiyu Li; Bei Yu 001 (AAAI, 2022)

Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper). - Hao Geng; Tinghuan Chen; Qi Sun 002; Bei Yu 001 (ASP-DAC, 2022)

PCL: Proxy-based Contrastive Learning for Domain Generalization. - Xufeng Yao; Yang Bai; Xinyun Zhang; Yuechen Zhang; Qi Sun 002; Ran Chen 001; Ruiyu Li; Bei Yu 001 (CVPR, 2022)

PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning. - Hao Geng; Qi Xu; Tsung-Yi Ho; Bei Yu 001 (DAC, 2022)

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. - Mingjun Li; Jianlei Yang 001; Yingjie Qi; Meng Dong; Yuhao Yang; Runze Liu 001; Weitao Pan; Bei Yu 001; Weisheng Zhao (DAC, 2022)

GTuner: tuning DNN computations on GPU via graph attention network. - Qi Sun 002; Xinyun Zhang; Hao Geng; Yuxuan Zhao 001; Yang Bai; Haisheng Zheng; Bei Yu 001 (DAC, 2022)

Functionality matters in netlist representation learning. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Bei Yu 001; Yu Huang 005 (DAC, 2022)

DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting. - Peiyu Liao; Siting Liu 002; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (DATE, 2022)

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler. - Siting Liu 002; Peiyu Liao; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (DATE, 2022)

Efficient Hotspot Detection via Graph Neural Network. - Shuyuan Sun; Yiyang Jiang; Fan Yang 001; Bei Yu 001; Xuan Zeng 001 (DATE, 2022)

Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems. - Haoyu Yang; Kit Fung; Yuxuan Zhao 001; Yibo Lin; Bei Yu 001 (DATE, 2022)

TRADER: A Practical Track-Assignment-Based Detailed Router. - Zhen Zhuang; Genggeng Liu; Tsung-Yi Ho; Bei Yu 001; Wenzhong Guo (DATE, 2022)

Efficient Point Cloud Analysis Using Hilbert Curve. - Wanli Chen; Xinge Zhu; Guojin Chen; Bei Yu 001 (ECCV (2), 2022)

X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. - Zhuolun He; Yuzhe Ma; Bei Yu 001 (ICCAD, 2022)

LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling. - Liangjian Wen; Yi Zhu 004; Lei Ye; Guojin Chen; Bei Yu 001; Jianzhuang Liu; Chunjing Xu (ICCAD, 2022)

AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns. - Wenqian Zhao; Xufeng Yao; Ziyang Yu 001; Guojin Chen; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ICCAD, 2022)

Multi-Package Co-Design for Chiplet Integration. - Zhen Zhuang; Bei Yu 001; Kai-Yuan Chao; Tsung-Yi Ho (ICCAD, 2022)

Efficient Design Rule Checking Script Generation via Key Information Extraction. - Binwu Zhu; Xinyun Zhang; Yibo Lin; Bei Yu 001; Martin D. F. Wong (MLCAD, 2022)

PVDD: A Practical Video Denoising Dataset with Real-World Dynamic Scenes. - Xiaogang Xu 002; Yitong Yu; Nianjuan Jiang; Jiangbo Lu; Bei Yu 001; Jiaya Jia (CoRR, 2022)

Rethinking Graph Neural Networks for the Graph Coloring Problem. - Wei Li 159; Ruxuan Li; Yuzhe Ma; Siu On Chan; David Z. Pan; Bei Yu 001 (CoRR, 2022)

Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. - Guyue Huang; Yang Bai; Liu Liu 017; Yuke Wang; Bei Yu 001; Yufei Ding 001; Yuan Xie 001 (CoRR, 2022)

DAMO: Deep Agile Mask Optimization for Full-Chip Scale. - Guojin Chen; Wanli Chen; Qi Sun 002; Yuzhe Ma; Haoyu Yang; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. - Tinghuan Chen; Qi Sun 002; Canhui Zhan; Changze Liu; Huatao Yu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Faster Region-Based Hotspot Detection. - Ran Chen 001; Wei Zhong; Haoyu Yang; Hao Geng; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

High-Speed Adder Design Space Exploration via Graph Neural Processes. - Hao Geng; Yuzhe Ma; Qi Xu; Jin Miao; Subhendu Roy; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hotspot Detection via Attention-Based Deep Layout Metric Learning. - Hao Geng; Haoyu Yang; Lu Zhang; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. - Bentian Jiang; Lixin Liu; Yuzhe Ma; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Pin-Accessible Legalization for Mixed-Cell-Height Circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Adaptive Layout Decomposition With Graph Embedding Neural Networks. - Wei Li 159; Yuzhe Ma; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. - Martin Rapp; Hussam Amrouch; Yibo Lin; Bei Yu 001; David Z. Pan; Marilyn Wolf; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Counteracting Adversarial Attacks in Autonomous Driving. - Qi Sun 002; Xufeng Yao; Arjun Ashok Rao; Bei Yu 001; Shiyan Hu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. - Xiaodong Wang; Changhao Yan; Yuzhe Ma; Bei Yu 001; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. - Qi Xu; Hao Geng; Tianming Ni; Song Chen 001; Bei Yu 001; Yi Kang; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. - Wei Zhong; Shuxiang Hu; Yuzhe Ma; Haoyu Yang; Xiuyuan Ma; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Sharing Grouped Convolution via Bayesian Learning. - Tinghuan Chen; Bin Duan; Qi Sun 002; Meng Zhang 010; Guoqing Li; Hao Geng; Qianru Zhang; Bei Yu 001 (IEEE Trans. Neural Networks Learn. Syst., 2022)

Efficient Layout Hotspot Detection via Neural Architecture Search. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. - Qi Sun 002; Tinghuan Chen; Siting Liu 002; Jianli Chen; Hao Yu 001; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution. - Yuxuan Zhao 001; Qi Sun 002; Zhuolun He; Yang Bai; Bei Yu 001 (AAAI, 2023)

OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper). - Su Zheng; Bei Yu 001; Martin D. F. Wong (ASICON, 2023)

Mixed-Type Wafer Failure Pattern Recognition. - Hao Geng; Qi Sun 002; Tinghuan Chen; Qi Xu; Tsung-Yi Ho; Bei Yu 001 (ASP-DAC, 2023)

Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (ASP-DAC, 2023)

Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. - Jianwang Zhai; Yici Cai; Bei Yu 001 (ASP-DAC, 2023)

Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. - Guojin Chen; Zehua Pei; Haoyu Yang; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration. - Zhuolun He; Yihang Zuo; Jiaxi Jiang; Haisheng Zheng; Yuzhe Ma; Bei Yu 001 (DAC, 2023)

On a Moreau Envelope Wirelength Model for Analytical Global Placement. - Peiyu Liao; Hongduo Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

Efficient ILT via Multi-level Lithography Simulation. - Shuyuan Sun; Fan Yang 001; Bei Yu 001; Li Shang; Xuan Zeng 001 (DAC, 2023)

Restructure-Tolerant Timing Prediction via Multimodal Fusion. - Ziyi Wang 010; Siting Liu 002; Yuan Pu 001; Song Chen 001; Tsung-Yi Ho; Bei Yu 001 (DAC, 2023)

DiffPattern: Layout Pattern Generation via Discrete Diffusion. - Zixiao Wang 001; Yunheng Shen; Wenqian Zhao; Yang Bai; Guojin Chen; Farzan Farnia; Bei Yu 001 (DAC, 2023)

LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition. - Yu Zhang 189; Yifan Chen; Zhonglin Xie; Hong Xu 001; Zaiwen Wen; Yibo Lin; Bei Yu 001 (DAC, 2023)

Mitigating Distribution Shift for Congestion Optimization in Global Placement. - Su Zheng; Lancheng Zou; Siting Liu 002; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. - Rongliang Fu; Junying Huang; Mengmeng Wang 006; Nobuyuki Yoshikawa; Bei Yu 001; Tsung-Yi Ho; Olivia Chen (DATE, 2023)

Fast and Accurate Wire Timing Estimation Based on Graph Learning. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (DATE, 2023)

Efficient Design Rule Checking with GPU Acceleration. - Wei Zhong; Zhenhua Feng; Zhuolun He; Weimin Wang; Yuzhe Ma; Bei Yu 001 (DATE, 2023)

ATFormer: A Learned Performance Model with Transfer Learning Across Devices for Deep Learning Tensor Programs. - Yang Bai; Wenqian Zhao; Shuo Yin; Zixiao Wang 001; Bei Yu 001 (EMNLP, 2023)

Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (ICCAD, 2023)

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. - Rongliang Fu; Olivia Chen; Bei Yu 001; Nobuyuki Yoshikawa; Tsung-Yi Ho (ICCAD, 2023)

Invited Paper: Heterogeneous Acceleration for Design Rule Checking. - Zhuolun He; Bei Yu 001 (ICCAD, 2023)

Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning. - Fuxing Huang; Duanxiang Liu; Xingquan Li; Bei Yu 001; Wenxing Zhu (ICCAD, 2023)

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. - Zehua Pei; Fangzhou Liu; Zhuolun He; Guojin Chen; Haisheng Zheng; Keren Zhu 001; Bei Yu 001 (ICCAD, 2023)

IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration. - Ziyang Yu 001; Chen Bai; Shoubo Hu; Ran Chen 001; Taohai He; Mingxuan Yuan; Bei Yu 001; Martin D. F. Wong (ICCAD, 2023)

Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. - Zhen Zhuang; Kai-Yuan Chao; Bei Yu 001; Tsung-Yi Ho; Martin D. F. Wong (ICCAD, 2023)

Efficient Deep Space Filling Curve. - Wanli Chen; Xufeng Yao; Xinyun Zhang; Bei Yu 001 (ICCV, 2023)

Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. - Peng Xu; Lin Zhang; Xuanzhou Liu; Jiaqi Sun; Yue Zhao 016; Haiqin Yang; Bei Yu 001 (ICML, 2023)

SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU. - Shui Jiang; Tsung-Wei Huang; Bei Yu 001; Tsung-Yi Ho (ICPP, 2023)

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IJCAI, 2023)

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. - Chen Bai; Jiayi Huang 001; Xuechao Wei; Yuzhe Ma; Sicheng Li 001; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (MICRO, 2023)

Machine Learning in EDA: When and How. - Bei Yu 001 (MLCAD, 2023)

ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs. - Guyue Huang; Yang Bai; Liu Liu 017; Yuke Wang; Bei Yu 001; Yufei Ding 001; Yuan Xie 001 (MLSys, 2023)

LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing. - Su Zheng; Haoyu Yang; Binwu Zhu; Bei Yu 001; Martin D. F. Wong (NeurIPS, 2023)

GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition. - Guojin Chen; Haoyu Yang; Bei Yu 001 (CoRR, 2023)

Towards Versatile and Efficient Visual Knowledge Injection into Pre-trained Language Models with Cross-Modal Adapters. - Xinyun Zhang; Haochen Tan; Han Wu 004; Mingjie Zhan; Ding Liang; Bei Yu 001 (CoRR, 2023)

Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. - Peng Xu; Lin Zhang; Xuanzhou Liu; Jiaqi Sun; Yue Zhao 016; Haiqing Yang; Bei Yu 001 (CoRR, 2023)

Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. - Peiyu Liao; Yuxuan Zhao 001; Dawei Guo; Yibo Lin; Bei Yu 001 (CoRR, 2023)

On the Evaluation of Generative Models in Distributed Learning Tasks. - Zixiao Wang 001; Farzan Farnia; Zhenghao Lin; Yunheng Shen; Bei Yu 001 (CoRR, 2023)

TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. - Jianlei Yang 001; Jiacheng Liao; Fanding Lei; Meichen Liu; Junyi Chen; Lingkun Long; Han Wan; Bei Yu 001; Weisheng Zhao (CoRR, 2023)

Adaptive Perspective Distillation for Semantic Segmentation. - Zhuotao Tian; Pengguang Chen; Xin Lai; Li Jiang 009; Shu Liu 005; Hengshuang Zhao; Bei Yu 001; Ming-Chang Yang; Jiaya Jia (IEEE Trans. Pattern Anal. Mach. Intell., 2023)

Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems. - Qi Xu; Junpeng Wang 002; Bo Yuan 006; Qi Sun 002; Song Chen 001; Bei Yu 001; Yi Kang; Feng Wu 001 (IEEE Trans Autom. Sci. Eng., 2023)

PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization. - Hao Geng; Tinghuan Chen; Yuzhe Ma; Binwu Zhu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. - Ziyi Wang 010; Zhuolun He; Chen Bai; Haoyu Yang; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Machine Learning in Advanced IC Design: A Methodological Survey. - Tinghuan Chen; Grace Li Zhang; Bei Yu 001; Bing Li 005; Ulf Schlichtmann (IEEE Des. Test, 2023)

Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA. - Ulf Schlichtmann; Bing Li 005; Bei Yu 001; Raviv Gal (IEEE Des. Test, 2023)

A GPU-Enabled Level-Set Method for Mask Optimization. - Ziyang Yu 001; Guojin Chen; Yuzhe Ma; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DSGN++: Exploiting Visual-Spatial Relation for Stereo-Based 3D Detectors. - Yilun Chen; Shijia Huang; Shu Liu 005; Bei Yu 001; Jiaya Jia (IEEE Trans. Pattern Anal. Mach. Intell., 2023)

A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation. - Ran Chen 001; Shoubo Hu; Zhitang Chen; Shengyu Zhu 001; Bei Yu 001; Pengyun Li; Cheng Chen; Yu Huang 005; Jianye Hao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. - Su Zheng; Hao Geng; Chen Bai; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2023)

DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. - Binwu Zhu; Xinyun Zhang; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2023)

Conditional Temporal Variational AutoEncoder for Action Video Prediction. - Xiaogang Xu 002; Yi Wang 074; Liwei Wang 009; Bei Yu 001; Jiaya Jia (Int. J. Comput. Vis., 2023)

TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks. - Tinghuan Chen; Silu Xiong; Huan He; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement. - Peiyu Liao; Dawei Guo; Zizheng Guo; Siting Liu 002; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation. - Ziyang Yu 001; Peiyu Liao; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. - Wenqian Zhao; Yang Bai; Qi Sun 002; Wenbo Li 002; Haisheng Zheng; Nianjuan Jiang; Jiangbo Lu; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DevelSet: Deep Neural Level Set for Instant Mask Optimization. - Guojin Chen; Ziyang Yu 001; Hongduo Liu; Yuzhe Ma; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Aging-Aware Critical Path Selection via Graph Attention Networks. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. - Chen Bai; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (AAAI, 2024)

p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models. - Haoyuan Wu; Xinyun Zhang; Peng Xu; Peiyu Liao; Xufeng Yao; Bei Yu 001 (AAAI, 2024)

Progressively Knowledge Distillation via Re-parameterizing Diffusion Reverse Process. - Xufeng Yao; Fanbin Lu; Yuechen Zhang; Xinyun Zhang; Wenqian Zhao; Bei Yu 001 (AAAI, 2024)

SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design. - Shixin Chen; Su Zheng; Chen Bai; Wenqian Zhao; Shuo Yin; Yang Bai; Bei Yu 001 (ASPDAC, 2024)

iEDA: An Open-source infrastructure of EDA. - Xingquan Li; Zengrong Huang; Simin Tao; Zhipeng Huang 009; Chunan Zhuang; Hao Wang; Yifan Li; Yihang Qiu; Guojie Luo; Huawei Li 001; Haihua Shen; Mingyu Chen 001; et al. (ASPDAC, 2024)

iPD: An Open-source intelligent Physical Design Toolchain. - Xingquan Li; Simin Tao; Shijian Chen; Zhisheng Zeng; Zhipeng Huang 009; Hongxi Wu; Weiguo Li; Zengrong Huang; Liwei Ni; Xueyan Zhao; He Liu; Shuaiying Long; et al. (ASPDAC, 2024)

Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). - Peng Xu; Jintao Li; Tsung-Yi Ho; Bei Yu 001; Keren Zhu 001 (ASPDAC, 2024)

V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting. - Ping Zhang; Pengju Yao; Xingquan Li; Bei Yu 001; Wenxing Zhu (ASPDAC, 2024)

LSTP: A Logic Synthesis Timing Predictor. - Haisheng Zheng; Zhuolun He; Fangzhou Liu; Zehua Pei; Bei Yu 001 (ASPDAC, 2024)

Classes Are Not Equal: An Empirical Study on Image Recognition Fairness. - Jiequan Cui; Beier Zhu; Xin Wen 004; Xiaojuan Qi 001; Bei Yu 001; Hanwang Zhang (CVPR, 2024)

Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection. - Yinuo Bai; Enxin Yi; Wei W. Xing; Bei Yu 001; Zhou Jin 001 (DAC, 2024)

Efficient Bilevel Source Mask Optimization. - Guojin Chen; Hongquan He; Peng Xu; Hao Geng; Bei Yu 001 (DAC, 2024)

PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry. - Jiaxi Jiang; Lancheng Zou; Wenqian Zhao; Zhuolun He; Tinghuan Chen; Bei Yu 001 (DAC, 2024)

G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner. - Wan-Luan Lee; Dian-Lun Lin; Tsung-Wei Huang; Shui Jiang; Tsung-Yi Ho; Yibo Lin; Bei Yu 001 (DAC, 2024)

Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree. - Weiguo Li; Zhipeng Huang 009; Bei Yu 001; Wenxing Zhu; Xingquan Li (DAC, 2024)

WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. - Mingjun Li; Pengjia Li; Shuo Yin; Shixin Chen; Beichen Li; Chong Tong; Jianlei Yang 001; Tinghuan Chen; Bei Yu 001 (DAC, 2024)

CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning. - Xiaoxiao Liang; Haoyu Yang; Kang Liu 017; Bei Yu 001; Yuzhe Ma (DAC, 2024)

NeuroSelect: Learning to Select Clauses in SAT Solvers. - Hongduo Liu; Peng Xu; Yuan Pu 001; Lihao Yin; Hui-Ling Zhen; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

Knowing The Spec to Explore The Design via Transformed Bayesian Optimization. - Donger Luo; Qi Sun 002; Xinheng Li; Chen Bai; Bei Yu 001; Hao Geng (DAC, 2024)

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. - Yuan Pu 001; Fangzhou Liu; Yu Zhang 189; Zhuolun He; Yibo Lin; Kai-Yuan Chao; Bei Yu 001 (DAC, 2024)

GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. - Tong Qiao; Jianlei Yang 001; Yingjie Qi; Ao Zhou; Chen Bai; Bei Yu 001; Weisheng Zhao; Chunming Hu (DAC, 2024)

Efficient ILT via Multigrid-Schwartz Method. - Shuyuan Sun; Fan Yang 001; Bei Yu 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

ChatPattern: Layout Pattern Customization via Natural Language. - Zixiao Wang 001; Yunheng Shen; Xufeng Yao; Wenqian Zhao; Yang Bai; Farzan Farnia; Bei Yu 001 (DAC, 2024)

Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. - Peng Xu; Guojin Chen; Keren Zhu 001; Tinghuan Chen; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer. - Xinyun Zhang; Su Zheng; Guojin Chen; Binwu Zhu; Hong Xu 001; Bei Yu 001 (DAC, 2024)

Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Ziyi Wang 010; Peng Xu; Hong Xu 001; Bei Yu 001 (DAC, 2024)

EMOGen: Enhancing Mask Optimization via Pattern Generation. - Su Zheng; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (DAC, 2024)

Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification. - Hongduo Liu; Peiyu Liao; Junhua Huang; Hui-Ling Zhen; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (DATE, 2024)

CBTune: Contextual Bandit Tuning for Logic Synthesis. - Fangzhou Liu; Zehua Pei; Ziyang Yu 001; Haisheng Zheng; Zhuolun He; Tinghuan Chen; Bei Yu 001 (DATE, 2024)

Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks. - Haoyuan Wu; Haisheng Zheng; Zhuolun He; Bei Yu 001 (EMNLP, 2024)

Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs. - Shan Shen; Dingcheng Yang; Yuyang Xie; Chunyan Pei; Bei Yu 001; Wenjian Yu (ACM Great Lakes Symposium on VLSI, 2024)

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. - Yuan Pu 001; Zhuolun He; Tairu Qiu; Haoyuan Wu; Bei Yu 001 (ICCAD, 2024)

PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network. - Jiawei Liu 006; Jianwang Zhai; Mingyu Zhao; Zhe Lin 001; Bei Yu 001; Chuan Shi 001 (ICCAD, 2024)

DiffSAT: Differential MaxSAT Layer for SAT Solving. - Yu Zhang 189; Hui-Ling Zhen; Mingxuan Yuan; Bei Yu 001 (ICCAD, 2024)

An Agile Framework for Efficient LLM Accelerator Development and Model Inference. - Lvcheng Chen; Ying Wu; Chenyi Wen; Shizhang Wang; Li Zhang 021; Bei Yu 001; Qi Sun 002; Cheng Zhuo (ICCAD, 2024)

Differentiable Edge-based OPC. - Guojin Chen; Haoyu Yang; Haoxing Mark Ren; Bei Yu 001; David Z. Pan (ICCAD, 2024)

Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization? - Yuanhang Gao; Donger Luo; Chen Bai; Bei Yu 001; Hao Geng; Qi Sun 002; Cheng Zhuo (ICCAD, 2024)

RISCSparse: Point Cloud Inference Engine on RISC-V Processor. - Shangran Lin; Xinrui Zhu; Baohui Xie; Tinghuan Chen; Cheng Zhuo; Qi Sun 002; Bei Yu 001 (ICCAD, 2024)

Peak Power and Dynamic IR-drop Assessment via Waveform Augmenting. - Yihan Wen; Juan Li; Bei Yu 001; Xiaoyi Wang (ICCAD, 2024)

RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization. - Peng Xu; Su Zheng; Yuyang Ye 001; Chen Bai; Siyuan Xu; Hao Geng; Tsung-Yi Ho; Bei Yu 001 (ICCAD, 2024)

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. - Xufeng Yao; Yiwen Wang; Xing Li; Yingzhao Lian; Ran Chen 001; Lei Chen 031; Mingxuan Yuan; Hong Xu 001; Bei Yu 001 (ICCAD, 2024)

Fed2Com: Towards Efficient Compression in Federated Learning. - Yu Zhang 189; Wei Lin; Sisi Chen; Qingyu Song 002; Jiaxun Lu; Yunfeng Shao 001; Bei Yu 001; Hong Xu 001 (ICNC, 2024)

BetterV: Controlled Verilog Generation with Discriminative Guidance. - Zehua Pei; Hui-Ling Zhen; Mingxuan Yuan; Yu Huang 005; Bei Yu 001 (ICML, 2024)

BiE: Bi-Exponent Block Floating-Point for Large Language Models Quantization. - Lancheng Zou; Wenqian Zhao; Shuo Yin; Chen Bai; Qi Sun 002; Bei Yu 001 (ICML, 2024)

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. - Siting Liu 002; Jiaxi Jiang; Zhuolun He; Ziyi Wang 010; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ISPD, 2024)

Large Language Models for EDA: Future or Mirage? - Zhuolun He; Bei Yu 001 (ISPD, 2024)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (ISPD, 2024)

FuILT: Full Chip ILT System With Boundary Healing. - Shuo Yin; Wenqian Zhao; Li Xie; Hong Chen; Yuzhe Ma; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2024)

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. - Yu Zhang 189; Yuan Pu 001; Fangzhou Liu; Peiyu Liao; Kai-Yuan Chao; Keren Zhu 001; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Decoupled Kullback-Leibler Divergence Loss. - Jiequan Cui; Zhuotao Tian; Zhisheng Zhong; Xiaojuan Qi 001; Bei Yu 001; Hanwang Zhang (NeurIPS, 2024)

Improving Neural ODE Training with Temporal Adaptive Batch Normalization. - Su Zheng; Zhengqi Gao; Fan-Keng Sun; Duane S. Boning; Bei Yu 001; Martin D. F. Wong (NeurIPS, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks. - Haoyuan Wu; Haisheng Zheng; Bei Yu 001 (CoRR, 2024)

SoLA: Solver-Layer Adaption of LLM for Better Logic Reasoning. - Yu Zhang 189; Hui-Ling Zhen; Zehua Pei; Yingzhao Lian; Lihao Yin; Mingxuan Yuan; Bei Yu 001 (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

Analytical Heterogeneous Die-to-Die 3D Placement with Macros. - Yuxuan Zhao 001; Peiyu Liao; Siting Liu 002; Jiaxi Jiang; Yibo Lin; Bei Yu 001 (CoRR, 2024)

HDLdebugger: Streamlining HDL debugging with Large Language Models. - Xufeng Yao; Haoyang Li 002; Tsz Ho Chan; Wenyi Xiao; Mingxuan Yuan; Yu Huang 005; Lei Chen 002; Bei Yu 001 (CoRR, 2024)

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. - Guojin Chen; Keren Zhu 001; Seunggeun Kim; Hanqing Zhu; Yao Lai; Bei Yu 001; David Z. Pan (CoRR, 2024)

MoreauPruner: Robust Pruning of Large Language Models against Weight Perturbations. - Zixiao Wang 001; Jingwei Zhang; Wenqian Zhao; Farzan Farnia; Bei Yu 001 (CoRR, 2024)

Open-Source Differentiable Lithography Imaging Framework. - Guojin Chen; Hao Geng; Bei Yu 001; David Z. Pan (CoRR, 2024)

The Survey of Chiplet-based Integrated Architecture: An EDA perspective. - Shixin Chen; Hengyuan Zhang; Zichao Ling; Jianwang Zhai; Bei Yu 001 (CoRR, 2024)

FuseGPT: Learnable Layers Fusion of Generative Pre-trained Transformers. - Zehua Pei; Hui-Ling Zhen; Xianzhi Yu; Sinno Jialin Pan; Mingxuan Yuan; Bei Yu 001 (CoRR, 2024)

MixPE: Quantization and Hardware Co-design for Efficient LLM Inference. - Yu Zhang 189; Mingzi Wang; Lancheng Zou; Wulong Liu; Hui-Ling Zhen; Mingxuan Yuan; Bei Yu 001 (CoRR, 2024)

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization. - Tinghuan Chen; Hao Geng; Qi Sun 002; Sanping Wan; Yongsheng Sun; Huatao Yu; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior. - Peng Xu; Siyuan Xu; Tinghuan Chen; Guojin Chen; Tsung-Yi Ho; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

RL-OPC: Mask Optimization With Deep Reinforcement Learning. - Xiaoxiao Liang; Yikang Ouyang; Haoyu Yang; Bei Yu 001; Yuzhe Ma (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning. - Yuyang Ye 001; Tinghuan Chen; Zicheng Wang; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. - Chen Bai; Qi Sun 002; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2024)

PFENet++: Boosting Few-Shot Semantic Segmentation With the Noise-Filtered Context-Aware Prior Mask. - Xiaoliu Luo; Zhuotao Tian; Taiping Zhang; Bei Yu 001; Yuan Yan Tang; Jiaya Jia (IEEE Trans. Pattern Anal. Mach. Intell., 2024)

GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores. - Yang Bai; Xufeng Yao; Qi Sun 002; Wenqian Zhao; Shixin Chen; Zixiao Wang 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. - Zhaoting Chen; Junzhe Cai; Changhao Yan; Zhaori Bi; Yuzhe Ma; Bei Yu 001; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

L2O-ILT: Learning to Optimize Inverse Lithography Techniques. - Binwu Zhu; Su Zheng; Ziyang Yu 001; Guojin Chen; Yuzhe Ma; Fan Yang 001; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Small is Beautiful: Compressing Deep Neural Networks for Partial Domain Adaptation. - Yuzhe Ma; Xufeng Yao; Ran Chen 001; Ruiyu Li; Xiaoyong Shen; Bei Yu 001 (IEEE Trans. Neural Networks Learn. Syst., 2024)

A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs. - Hongduo Liu; Yijian Qian; Youqiang Liang; Bin Zhang; Zhaohan Liu; Tao He; Wenqian Zhao; Jiangbo Lu; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. - Bo Yang; Qi Xu; Hao Geng; Song Chen 001; Bei Yu 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2024)

Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. - Shixin Chen; Shanyi Li; Zhen Zhuang; Su Zheng; Zheng Liang 003; Tsung-Yi Ho; Bei Yu 001; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. - Peiyu Liao; Yuxuan Zhao 001; Dawei Guo; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. - Guojin Chen; Zixiao Wang 001; Bei Yu 001; David Z. Pan; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers. - Wenqian Zhao; Xufeng Yao; Shuo Yin; Yang Bai; Ziyang Yu 001; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. - Haoyuan Wu; Zhuolun He; Xinyun Zhang; Xufeng Yao; Su Zheng; Haisheng Zheng; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Generalized Parametric Contrastive Learning. - Jiequan Cui; Zhisheng Zhong; Zhuotao Tian; Shu Liu 005; Bei Yu 001; Jiaya Jia (IEEE Trans. Pattern Anal. Mach. Intell., 2024)

Quantization via Distillation and Contrastive Learning. - Zehua Pei; Xufeng Yao; Wenqian Zhao; Bei Yu 001 (IEEE Trans. Neural Networks Learn. Syst., 2024)

Intelligent OPC Engineer Assistant for Semiconductor Manufacturing. - Guojin Chen; Haoyu Yang; Bei Yu 001; Haoxing Ren (AAAI, 2025)

FlexPose: Pose Distribution Adaptation with Limited Guidance. - Zixiao Wang; Junwu Weng; Mengyuan Liu; Bei Yu 001 (AAAI, 2025)

Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts. - Haoyuan Wu; Rui Ming; Haisheng Zheng; Zhuolun He; Bei Yu 001 (ACL (1), 2025)

PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement. - Lin Chen 029; Ran Chen 001; Shoubo Hu; Xufeng Yao; Zhentao Tang; Shixiong Kai; Siyuan Xu; Mingxuan Yuan; Jianye Hao; Bei Yu 001; Jiang Xu 001 (ASP-DAC, 2025)

The Survey of 2.5D Integrated Architecture: An EDA perspective. - Shixin Chen; Hengyuan Zhang; Zichao Ling; Jianwang Zhai; Bei Yu 001 (ASP-DAC, 2025)

FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. - Zirui Li; Kanglin Tian; Jianwang Zhai; Zixuan Li; Shixiong Kai; Siyuan Xu; Bei Yu 001; Kang Zhao (ASP-DAC, 2025)

ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator. - Xinfei Liu; Siting Liu 002; Bei Yu 001; Song Chen 001; Qi Xu (ASP-DAC, 2025)

Generative Video Propagation. - Shaoteng Liu; Tianyu Wang 003; Jui-Hsien Wang; Qing Liu 017; Zhifei Zhang; Joon-Young Lee; Yijun Li 001; Bei Yu 001; Zhe Lin 001; Soo Ye Kim; Jiaya Jia (CVPR, 2025)

DreamOmni: Unified Image Generation and Editing. - Bin Xia; Yuechen Zhang; Jingyao Li; Chengyao Wang; Yitong Wang; Xinglong Wu; Bei Yu 001; Jiaya Jia (CVPR, 2025)

VisionZip: Longer is Better but Not Necessary in Vision Language Models. - Senqiao Yang; Yukang Chen; Zhuotao Tian; Chengyao Wang; Jingyao Li; Bei Yu 001; Jiaya Jia (CVPR, 2025)

IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning. - Feng Guo; Jianwang Zhai; Jingyu Jia; Jiawei Liu 006; Kang Zhao; Bei Yu 001; Chuan Shi 001 (DATE, 2025)

Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer. - Xiangfei Hu; Yuyang Ye 001; Tinghuan Chen; Hao Yan 002; Bei Yu 001 (DATE, 2025)

LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language Model. - Tianyi Li; Zhexin Tang; Tao Wu; Bei Yu 001; Jingyi Yu; Hao Geng (DATE, 2025)

WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction. - Jiawei Liu 006; Zhiyan Liu; Xun He; Jianwang Zhai; Zhengyuan Shi; Qiang Xu 001; Bei Yu 001; Chuan Shi 001 (DATE, 2025)

iRw: An Intelligent Rewriting. - Haisheng Zheng; Haoyuan Wu; Zhuolun He; Yuzhe Ma; Bei Yu 001 (DATE, 2025)

Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment. - Haoyuan Wu; Haisheng Zheng; Yuan Pu 001; Bei Yu 001 (ICLR, 2025)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)

Invited: Physical Design for Advanced 3D ICs: Challenges and Solutions. - Yuxuan Zhao 001; Lancheng Zou; Bei Yu 001 (ISPD, 2025)

GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays. - Fangzhou Liu; Guannan Guo; Yuyang Ye 001; Ziyi Wang 010; Wenjie Fu 003; Weihua Sheng; Bei Yu 001 (ISPD, 2025)

ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs. - Zheng Yang; Zhen Zhuang; Bei Yu 001; Tsung-Yi Ho; Martin D. F. Wong; Sung Kyu Lim (ISPD, 2025)

Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation. - Haoyuan Wu; Haisheng Zheng; Zhuolun He; Bei Yu 001 (NAACL (Long Papers), 2025)

Large Language Models for EDA: From Assistants to Agents. - Zhuolun He; Yuan Pu 001; Haoyuan Wu; Yuhan Qiu; Tairu Qiu; Bei Yu 001 (Found. Trends Electron. Des. Autom., 2025)

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Yu Huang 005; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

CMoE: Fast Carving of Mixture-of-Experts for Efficient LLM Inference. - Zehua Pei; Lancheng Zou; Hui-Ling Zhen; Xianzhi Yu; Wulong Liu; Sinno Jialin Pan; Mingxuan Yuan; Bei Yu 001 (CoRR, 2025)

TorchResist: Open-Source Differentiable Resist Simulator. - Zixiao Wang; Jieya Zhou; Su Zheng; Shuo Yin; Kaichao Liang; Shoubo Hu; Xiao Chen; Bei Yu 001 (CoRR, 2025)

Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table. - Haoyuan Wu; Haisheng Zheng; Shoubo Hu; Zhuolun He; Bei Yu 001 (CoRR, 2025)

Analytical Heterogeneous Die-to-Die 3-D Placement With Macros. - Yuxuan Zhao 001; Peiyu Liao; Siting Liu 002; Jiaxi Jiang; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Effective LLM Knowledge Learning via Model Generalization. - Mingkang Zhu; Xi Chen; Zhongdao Wang; Bei Yu 001; Hengshuang Zhao; Jiaya Jia (CoRR, 2025)

Seg-Zero: Reasoning-Chain Guided Segmentation via Cognitive Reinforcement. - Yuqi Liu 003; Bohao Peng; Zhisheng Zhong; Zihao Yue; Fanbin Lu; Bei Yu 001; Jiaya Jia (CoRR, 2025)

Generalized Kullback-Leibler Divergence Loss. - Jiequan Cui; Beier Zhu; Qingshan Xu 001; Zhuotao Tian; Xiaojuan Qi 001; Bei Yu 001; Hanwang Zhang; Richang Hong (CoRR, 2025)

Modular Customization of Diffusion Models via Blockwise-Parameterized Low-Rank Adaptation. - Mingkang Zhu; Xi Chen; Zhongdao Wang; Bei Yu 001; Hengshuang Zhao; Jiaya Jia (CoRR, 2025)

Does Your Vision-Language Model Get Lost in the Long Video Sampling Dilemma? - Tianyuan Qu; Longxiang Tang; Bohao Peng; Senqiao Yang; Bei Yu 001; Jiaya Jia (CoRR, 2025)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. - Xun Jiang 002; Haoran Lu; Yuxuan Zhao 001; Jiarui Wang; Zizheng Guo; Heng Wu 007; Bei Yu 001; Sung Kyu Lim; Runsheng Wang; Ru Huang 001; Yibo Lin (CoRR, 2025)

Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. - Rongliang Fu; Mengmeng Wang 006; Yirong Kan; Olivia Chen; Nobuyuki Yoshikawa; Bei Yu 001; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Layout Decomposition via Boolean Satisfiability. - Hongduo Liu; Peiyu Liao; Mengchuan Zou; Bowen Pang; Xijun Li; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling. - Ziyi Wang 010; Wenqian Zhao; Yuan Pu 001; Lei Chen 031; Wilson W. K. Thong; Weihua Sheng; Tsung-Yi Ho; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Evolution of Optimization Algorithms for Global Placement via Large Language Models. - Xufeng Yao; Jiaxi Jiang; Yuxuan Zhao 001; Peiyu Liao; Yibo Lin; Bei Yu 001 (CoRR, 2025)

BAQE: Backend-Adaptive DNN Deployment via Synchronous Bayesian Quantization and Hardware Configuration Exploration. - Wenqian Zhao; Shuo Yin; Chen Bai; Zixiao Wang 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion. - Zixiao Wang 001; Wenqian Zhao; Yunheng Shen; Yang Bai; Guojin Chen; Farzan Farnia; Bei Yu 001 (CoRR, 2025)

UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings. - Jiajun Qin; Yuan Pu 001; Zhuolun He; Seunggeun Kim; David Z. Pan; Bei Yu 001 (CoRR, 2025)

VisionReasoner: Unified Visual Perception and Reasoning via Reinforcement Learning. - Yuqi Liu 003; Tianyuan Qu; Zhisheng Zhong; Bohao Peng; Shu Liu 005; Bei Yu 001; Jiaya Jia (CoRR, 2025)

ToTRL: Unlock LLM Tree-of-Thoughts Reasoning Potential through Puzzles Solving. - Haoyuan Wu; Xueyi Chen; Rui Ming; Jilong Gao; Shoubo Hu; Zhuolun He; Bei Yu 001 (CoRR, 2025)

On-Policy Optimization with Group Equivalent Preference for Multi-Programming Language Understanding. - Haoyuan Wu; Rui Ming; Jilong Gao; Hangyu Zhao; Xueyi Chen; Yikai Yang; Haisheng Zheng; Zhuolun He; Bei Yu 001 (CoRR, 2025)

PreMoe: Lightening MoEs on Constrained Memory by Expert Pruning and Retrieval. - Zehua Pei; Yingchun Zhang; Hui-Ling Zhen; Xianzhi Yu; Wulong Liu; Sinno Jialin Pan; Mingxuan Yuan; Bei Yu 001 (CoRR, 2025)

RTime-QA: A Benchmark for Atomic Temporal Event Understanding in Large Multi-modal Models. - Yuqi Liu 003; Qin Jin; Tianyuan Qu; Xuan Liu; Yang Du; Bei Yu 001; Jiaya Jia (CoRR, 2025)

SwingArena: Competitive Programming Arena for Long-context GitHub Issue Solving. - Wendong Xu; Jing Xiong; Chenyang Zhao; Qiujiang Chen; Haoran Wang; Hui Shen; Zhongwei Wan; Jianbo Dai; Taiqiang Wu; He Xiao; Chaofan Tao; Z. Morley Mao; et al. (CoRR, 2025)

Sign-Off Timing Considerations via Concurrent Routing Topology Optimization. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Delay-Driven Rectilinear Steiner Tree Construction. - Hongxi Wu; Xingquan Li; Liang Chen 025; Bei Yu 001; Wenxing Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing. - Yuyang Ye 001; Peng Xu; Lizheng Ren; Tinghuan Chen; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine. - Ziyang Yu 001; Su Zheng; Wenqian Zhao; Shuo Yin; Xiaoxiao Liang; Guojin Chen; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling. - Jiahao Xu; Zhuolun He; Shuo Yin; Yuan Pu 001; Wenjian Yu; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

TGDPO: Harnessing Token-Level Reward Guidance for Enhancing Direct Preference Optimization. - Mingkang Zhu; Xi Chen; Zhongdao Wang; Bei Yu 001; Hengshuang Zhao; Jiaya Jia (CoRR, 2025)

VisionThink: Smart and Efficient Vision Language Model via Reinforcement Learning. - Senqiao Yang; Junyi Li; Xin Lai; Bei Yu 001; Hengshuang Zhao; Jiaya Jia (CoRR, 2025)

Generative Distribution Distillation. - Jiequan Cui; Beier Zhu; Qingshan Xu 001; Xiaogang Xu 002; Pengguang Chen; Xiaojuan Qi 001; Bei Yu 001; Hanwang Zhang; Richang Hong (CoRR, 2025)

Prerouting Timing Prediction Across Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Jiaxi Jiang; Ziyi Wang 010; Peng Xu; Hong Xu 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. - Lancheng Zou; Su Zheng; Peng Xu; Siting Liu 002; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization. - Wenqian Zhao; Lancheng Zou; Zixiao Wang 001; Xufeng Yao; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling. - Binwu Zhu; Su Zheng; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2025)

AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs. - Yao Lai; Souradip Poddar; Sungyoung Lee 004; Guojin Chen; Mengkang Hu; Bei Yu 001; Ping Luo 002; David Z. Pan (CoRR, 2025)

DreamVE: Unified Instruction-based Image and Video Editing. - Bin Xia; Jiyang Liu; Yuechen Zhang; Bohao Peng; Ruihang Chu; Yitong Wang; Xinglong Wu; Bei Yu 001; Jiaya Jia (CoRR, 2025)

TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. - Rongliang Fu; Chao Wang; Bei Yu 001; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Jiajun Qin; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning. - Mingjun Cheng; Shihan Zhang; Xin Zheng 001; Xian Lin; Huaien Gao; Shuting Cai; Xiaoming Xiong; Bei Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Learned Performance Model With Transfer Learning Across GPUs on Tensorized Instructions. - Yang Bai; Mingjun Li; Wendong Xu; Bei Yu 001 (IEEE Trans. Parallel Distributed Syst., 2025)