Efficient synthesis of distributed vector multipliers. - Béla Fehér (Microprocess. Microprogramming, 1993)

Cost Effective 2×2 Inner Product Processors. - Béla Fehér; Gábor Szedö (FPL, 1998)

Neural network implementation using distributed arithmetic. - Tamás Szabó; Béla Fehér; Gábor Horváth 001 (KES (3), 1998)

A Full-Parallel Digital Implementation for Pre-Trained NNs. - Tamás Szabó; Lörinc Antoni; Gábor Horváth 001; Béla Fehér (IJCNN (2), 2000)

Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. - Lörinc Antoni; Régis Leveugle; Béla Fehér (DFT, 2002)

Dependability Analysis: A New Application for Run-Time Reconfiguration. - Régis Leveugle; Lörinc Antoni; Béla Fehér (IPDPS, 2003)

3D rendering using FPGAs. - Péter Szántó; Béla Fehér (VLSI-SOC, 2003)

Using run-time reconfiguration for fault injection applications. - Lörinc Antoni; Régis Leveugle; Béla Fehér (IEEE Trans. Instrum. Meas., 2003)

High performance visibility testing with screen segmentation. - Péter Szántó; Béla Fehér (ESTIMedia, 2004)

Heuristic Automation for Decluttering Tactical Displays. - Mark F. St. John; Harvey S. Smallman; Daniel I. Manes; Béla Fehér; Jeffrey G. Morrison (Hum. Factors, 2005)

Acoustic Source Localization Fusing Sparse Direction of Arrival Estimates. - Ákos Lédeczi; Gergely Kis; Béla Fehér; Péter Völgyesi; György Balogh (WISES, 2006)

High-Performance Timing-Driven Rank Filter. - Péter Szántó; Gábor Szedö; Béla Fehér (VLSI Design, 2008)

LOGSYS: A simple tool for complex student projects. - Béla Fehér; Tamás Raikovich; György Dancsi; Péter Laczkó (MSE, 2009)

Molecular Docking on FPGA and GPU Platforms. - Imre Pechan; Béla Fehér (FPL, 2011)