A Reconfigurable Arithmetic Processor. - Arjun Rajagopal; Belli Kuttanna; Balaji Janakiraman; Rajarshi Mukherjee; Joy Shetler (VLSI Design, 1993)

A New PowerPC Microprocessor for Low Power Computing Systems. - Deene Ogden; Belli Kuttanna; Albert J. Loper; Soummya Mallick; Michael Putrino (COMPCON, 1995)

A G3 PowerPC™ superscalar low-power microprocessor. - A. Richard Kennedy; Mike Alexander; Eric Fiene; Jose A. Lyon; Belli Kuttanna; Rajesh Patel; Mydung N. Pham; Michael Putrino; Cody Croxton; Suzanne Litch; Brad Burgess (COMPCON, 1997)

Thermal management system for high performance PowerPC™ microprocessors. - Hector Sanchez; Belli Kuttanna; Tim Olson; Mike Alexander; Gianfranco Gerosa; Ross Philip; Jose Alvarez (COMPCON, 1997)

A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS. - Gianfranco Gerosa; Steve Curtis; Michael D'Addeo; Bo Jiang; Belliappa Kuttanna; Feroze Merchant; Binta Patel; Mohammed H. Taufique; Haytham Samarchi (ISSCC, 2008)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS. - Gianfranco Gerosa; Steve Curtis; Michael D'Addeo; Bo Jiang; Belliappa Kuttanna; Feroze Merchant; Binta Patel; Mohammed H. Taufique; Haytham Samarchi (IEEE J. Solid State Circuits, 2009)

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. - Guilherme Ottoni; Thomas Hartin; Christopher T. Weaver; Jason Brandt; Belliappa Kuttanna; Hong Wang 003 (Conf. Computing Frontiers, 2011)

Intel Atom C2000 Processor Family: Power-Efficient Datacenter Processing. - Bradley Burres; Johan van de Groenendaal; Praveen Mosur; Jonathan Robinson; Ian M. Steiner; Yi-Feng Liu; Sin S. Tan; Erik McShane; Belliappa Kuttanna; Sridhar Lakshmanamurthy (IEEE Micro, 2015)

Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. - Dipan Kumar Mandal; Srivatsava Jandhyala; Om Ji Omer; Gurpreet S. Kalsi; Biji George; Gopi Neela; Santhosh Kumar Rethinagiri; Sreenivas Subramoney; Lance Hacking; Jim Radford; Eagle Jones; Belliappa Kuttanna; et al. (DATE, 2019)

Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute. - Anant V. Nori; Rahul Bera; Shankar Balachandran; Joydeep Rakshit; Om Ji Omer; Avishaii Abuhatzera; Belliappa Kuttanna; Sreenivas Subramoney (CoRR, 2020)

REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute. - Anant V. Nori; Rahul Bera; Shankar Balachandran; Joydeep Rakshit; Om Ji Omer; Avishaii Abuhatzera; Belliappa Kuttanna; Sreenivas Subramoney (ISCA, 2021)