Fault Diagnosis of Digital Systems - A Review. - Ben Bennetts; D. W. Lewin (Comput. J., 1971)

An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks. - R. G. Bennetts (IEEE Trans. Computers, 1971)

A realistic approach to detection test generation for combinatorial logic circuits. - R. G. Bennetts (Comput. J., 1972)

Recent Developments in the Theory and Practice of Testable Logic Design. - R. G. Bennetts; Roy V. Scott (Computer, 1976)

Fault tolerance and digital systems. - R. G. Bennetts (Microprocess. Microsystems, 1979)

Digital test text caters for academia and researchers: Hideo Fujiwara 'Logic testing and design for testability' MIT Press, Cambridge, MA, USA (1985) £34.95 pp x + 284. - R. G. Bennetts (Microprocess. Microsystems, 1986)

Test Technology in Europe. - Ben Bennetts (IEEE Des. Test Comput., 1990)

Scan Technology at Work. - R. G. Bennetts (Fault-Tolerant Computing Systems, 1991)

IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status. - R. G. Bennetts; A. Osseyran (J. Electron. Test., 1991)

Progress in DFT: A Personal View. - Ben Bennetts (ITC, 1992)

Macro Testability: The Results of Production Device Applications. - Frank Bouwman; Steven Oostdijk; Rudi Stans; Ben Bennetts; Frans P. M. Beenker (ITC, 1992)

Essential reading for the basics and implementation of boundary scan: Parker, K PThe boundary-scan handbook Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9270 1, £48.00/Dfl. 160.00, pp 282. - Ben Bennetts (Microprocess. Microsystems, 1993)

Guest Editor's Introduction. - Ben Bennetts (IEEE Des. Test Comput., 1995)

Built-In Self-Test: Assuring System Integrity. - Bernd Könemann; Ben Bennetts; Najmi T. Jarwala; Benoit Nadeau-Dostie (Computer, 1996)

Guest Editors' Introduction: Test and the Product Life Cycle. - Tony Ambler; Ben Bennetts (IEEE Des. Test Comput., 1999)

Boundary Scan: The Internet of Test. - Mike Wondolowski; Ben Bennetts; Adam W. Ley (IEEE Des. Test Comput., 1999)

Guest Editors' Introduction: Board Test. - Monica Lobetti Bodoni; Ben Bennetts (IEEE Des. Test Comput., 2003)

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. - Erik Jan Marinissen; Bart Vermeulen; Henk D. L. Hollmann; Ben Bennetts (IEEE Des. Test Comput., 2003)

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. - Stephen K. Sunter; Adam Osseiran; Adam Cron; Neil G. Jacobson; Dave Bonnett; Bill Eklow; Carl Barnhart; Ben Bennetts (DATE, 2004)

IJTAG (internal JTAG): a step toward a DFT standard. - Jeff Rearick; Bill Eklow; Ken Posse; Al Crouch; Ben Bennetts (ITC, 2005)

New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG). - Bill Eklow; Ben Bennetts (ETS, 2006)

IEEE P1687: Toward Standardized Access of Embedded Instrumentation. - Ken Posse; Al Crouch; Jeff Rearick; Bill Eklow; Mike Laisne; Ben Bennetts; Jason Doege; Mike Ricchetti; Jean-Francois Cote (ITC, 2006)

Electronics Design-for-Test: Past, Present and Future. - Ben Bennetts (ETS, 2007)