Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. - Ben C. Drerup; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1994)

The PERCS High-Performance Interconnect. - L. Baba Arimilli; Ravi Arimilli; Vicente Chung; Scott Clark; Wolfgang E. Denzel; Ben C. Drerup; Torsten Hoefler; Jody B. Joyner; Jerry Lewis; Jian Li 059; Nan Ni; Ramakrishnan Rajamony (Hot Interconnects, 2010)

IBM POWER9 processor and system features for computing in the cognitive era. - L. Baba Arimilli; Bart Blaner; Ben C. Drerup; Charles F. Marino; Derek Williams; Eric N. Lais; Francesco A. Campisano; Guy L. Guthrie; Michael S. Floyd; Ross Leavens; Scot M. Willenborg; Ronald N. Kalla; et al. (IBM J. Res. Dev., 2018)