Experiences with a Model for Parallel Computation. - Ben H. H. Juurlink; Harry A. G. Wijshoff (PODC, 1993)

The Parallel Hierarchical Memory Model. - Ben H. H. Juurlink; Harry A. G. Wijshoff (SWAT, 1994)

Worm-Hole Gossiping on Meshes. - Ben H. H. Juurlink; P. S. Rao; Jop F. Sibeyn (Euro-Par, Vol. I, 1996)

The E-BSP Model: Incorporating General Locality and Unbalanced Communication into the BSP Model. - Ben H. H. Juurlink; Harry A. G. Wijshoff (Euro-Par, Vol. II, 1996)

Communication Primitives for BSP Computers. - Ben H. H. Juurlink; Harry A. G. Wijshoff (Inf. Process. Lett., 1996)

Experimental Validation of Parallel Computation Models on the Intel Paragon. - Ben H. H. Juurlink (IPPS/SPDP, 1998)

Communication-Optimal Parallel Minimum Spanning Tree Algorithms (Extended Abstract). - Micah Adler; Wolfgang Dittrich; Ben H. H. Juurlink; Miroslaw Kutylowski; Ingo Rieping (SPAA, 1998)

A Quantitative Comparison of Parallel Computation Models. - Ben H. H. Juurlink; Harry A. G. Wijshoff (ACM Trans. Comput. Syst., 1998)

Gossiping on Meshes and Tori. - Ben H. H. Juurlink; Jop F. Sibeyn; P. S. Rao (IEEE Trans. Parallel Distributed Syst., 1998)

The Paderborn University BSP (PUB) Library - Design, Implementation and Performance. - Olaf Bonorden; Ben H. H. Juurlink; Ingo von Otte; Ingo Rieping (IPPS/SPDP, 1999)

Counter Based Superscalar Instruction Issuing. - Sorin Cotofana; Ben H. H. Juurlink; Stamatis Vassiliadis (EUROMICRO, 2000)

Complex Streamed Instructions: Introduction and Initial Evaluatio. - Stamatis Vassiliadis; Ben H. H. Juurlink; Edwin A. Hakkennes (EUROMICRO, 2000)

Implementation and Evaluation of the Complex Streamed Instruction Set. - Ben H. H. Juurlink; Stamatis Vassiliadis; Dmitri Tcheressiz; Harry A. G. Wijshoff (IEEE PACT, 2001)

Performance of the Complex Streamed Instruction Set on Image Processing Kernels. - Dmitri Tcheressiz; Ben H. H. Juurlink; Stamatis Vassiliadis; Harry A. G. Wijshoff (Euro-Par, 2001)

Performance Scalability of Multimedia Instruction Set Extensions. - Dmitry Cheresiz; Ben H. H. Juurlink; Stamatis Vassiliadis; Harry A. G. Wijshoff (Euro-Par, 2002)

Architectural Support for 3D Graphics in the Complex Streamed Instruction Set. - Dmitry Cheresiz; Ben H. H. Juurlink; Stamatis Vassiliadis; Harry A. G. Wijshoff (IASTED PDCS, 2002)

Unified Dual Data Caches. - Ben H. H. Juurlink (DSD, 2003)

Optimal broadcast on parallel locality models. - Ben H. H. Juurlink; Petr Kolman; Friedhelm Meyer auf der Heide; Ingo Rieping (J. Discrete Algorithms, 2003)

Implementation of a streaming execution unit. - Dmitry Cheresiz; Ben H. H. Juurlink; Stamatis Vassiliadis; Harry A. G. Wijshoff (J. Syst. Archit., 2003)

The Paderborn University BSP (PUB) library. - Olaf Bonorden; Ben H. H. Juurlink; Ingo von Otte; Ingo Rieping (Parallel Comput., 2003)

Accelerating the secure remote password protocol using reconfigurable hardware. - Peter Groen; Panu Hämäläinen; Ben H. H. Juurlink; Timo Hämäläinen 001 (Conf. Computing Frontiers, 2004)

Approximating the optimal replacement algorithm. - Ben H. H. Juurlink (Conf. Computing Frontiers, 2004)

Dynamic techniques to reduce memory traffic in embedded systems. - Ben H. H. Juurlink; Pepijn J. de Langen (Conf. Computing Frontiers, 2004)

Reducing traffic generated by conflict misses in caches. - Pepijn J. de Langen; Ben H. H. Juurlink (Conf. Computing Frontiers, 2004)

Scene Management Models and Overlap Tests for Tile-Based Rendering. - Iosif Antochi; Ben H. H. Juurlink; Stamatis Vassiliadis; Petri Liuha (DSD, 2004)

Sparse Matrix Transpose Unit. - Pyrrhos Stathis; Dmitry Cheresiz; Stamatis Vassiliadis; Ben H. H. Juurlink (IPDPS, 2004)

Efficient tile-aware bounding-box overlap test for tile-based rendering. - Iosif Antochi; Bernardus Juurlink; Stamatis Vassiliadis; Petri Liuha (SoC, 2004)

GraalBench: a 3D graphics benchmark suite for mobile phones. - Iosif Antochi; Ben H. H. Juurlink; Stamatis Vassiliadis; Petri Liuha (LCTES, 2004)

Memory Bandwidth Requirements of Tile-Based Rendering. - Iosif Antochi; Ben H. H. Juurlink; Stamatis Vassiliadis; Petri Liuha (SAMOS, 2004)

Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (ASAP, 2005)

Matrix register file and extended subwords: two techniques for embedded media processors. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (Conf. Computing Frontiers, 2005)

Implementing Hardware Multithreading in a VLIW Architecture. - Stephan Suijkerbuijk; Ben H. H. Juurlink (IASTED PDCS, 2005)

Avoiding data conversions in embedded media processors. - Ben H. H. Juurlink; Asadollah Shahbahrami; Stamatis Vassiliadis (SAC, 2005)

The CSI multimedia architecture. - Dmitry Cheresiz; Ben H. H. Juurlink; Stamatis Vassiliadis; Harry A. G. Wijshoff (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (CASES, 2006)

Improving the memory behavior of vertical filtering in the discrete wavelet transform. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (Conf. Computing Frontiers, 2006)

Leakage-aware multiprocessor scheduling for low power. - Pepijn J. de Langen; Ben H. H. Juurlink (IPDPS, 2006)

Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (ISM, 2006)

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures. - Asadollah Shahbahrami; Ben H. H. Juurlink; Demid Borodin; Stamatis Vassiliadis (Int. J. Parallel Program., 2006)

SIMD Vectorization of Histogram Functions. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (ASAP, 2007)

Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool. - Jie Tao 001; Asadollah Shahbahrami; Ben H. H. Juurlink; Rainer Buchty; Wolfgang Karl; Stamatis Vassiliadis (ISM, 2007)

Instruction-Level Fault Tolerance Configurability. - Demid Borodin; Ben H. H. Juurlink; Stamatis Vassiliadis (ICSAMOS, 2007)

Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors. - Pepijn J. de Langen; Ben H. H. Juurlink (SAMOS, 2007)

Memory copies in multi-level memory systems. - Pepijn J. de Langen; Ben H. H. Juurlink (ASAP, 2008)

A Low-Cost Cache Coherence Verification Method for Snooping Systems. - Demid Borodin; Ben H. H. Juurlink (DSD, 2008)

Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic; Arnaldo Azevedo; Ben H. H. Juurlink (DSD, 2008)

(When) Will CMPs Hit the Power Wall?. - Cor Meenderinck; Ben H. H. Juurlink (Euro-Par Workshops, 2008)

Analysis of video filtering on the cell processor. - Arnaldo Azevedo; Cor Meenderinck; Ben H. H. Juurlink; Mauricio Alvarez 001; Alex Ramírez (ISCAS, 2008)

Optimization of Content-Based Image Retrieval Functions. - Asadollah Shahbahrami; Ben H. H. Juurlink (ISM, 2008)

GRAAL: A Framework for Low-Power 3D Graphics Accelerators. - Ben H. H. Juurlink; Iosif Antochi; Dan Crisu; Sorin Cotofana; Stamatis Vassiliadis (IEEE Computer Graphics and Applications, 2008)

Versatility of extended subwords and the matrix register file. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (ACM Trans. Archit. Code Optim., 2008)

Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors. - Asadollah Shahbahrami; Ben H. H. Juurlink; Stamatis Vassiliadis (IEEE Trans. Multim., 2008)

Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. - Asadollah Shahbahrami; Ben H. H. Juurlink (APPT, 2009)

Scalar Processing Overhead on SIMD-Only Architectures. - Arnaldo P. Azevedo Filho; Ben H. H. Juurlink (ASAP, 2009)

Specialization of the Cell SPE for Media Applications. - Cor Meenderinck; Ben H. H. Juurlink (ASAP, 2009)

Limiting the number of dirty cache lines. - Pepijn J. de Langen; Ben H. H. Juurlink (DATE, 2009)

Instruction Precomputation for Fault Detection. - Demid Borodin; Ben H. H. Juurlink; Stefanos Kaxiras (DSD, 2009)

SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. - Asadollah Shahbahrami; Ben H. H. Juurlink (DSD, 2009)

The 3TU embedded systems master in the Netherlands. - Gerard J. M. Smit; Gerrit F. van der Hoeven; Jan Friso Groote; Ralph H. J. M. Otten; Hans Tonino; Ben H. H. Juurlink; Boudewijn R. H. M. Haverkort (WESE@ESWEEK, 2009)

Introduction. - Pedro C. Diniz; Ben H. H. Juurlink; Alain Darte; Wolfgang Karl (Euro-Par, 2009)

Parallel H.264 Decoding on an Embedded Multicore Processor. - Arnaldo Azevedo; Cor Meenderinck; Ben H. H. Juurlink; Andrei Sergeevich Terechko; Jan Hoogerbrugge; Mauricio Alvarez 001; Alex Ramírez (HiPEAC, 2009)

Intra-vector SIMD instructions for core specialization. - Cor Meenderinck; Ben H. H. Juurlink (ICCD, 2009)

Scalability of Macroblock-level Parallelism for H.264 Decoding. - Mauricio Alvarez-Mesa; Alex Ramírez; Arnaldo Azevedo; Cor Meenderinck; Ben H. H. Juurlink; Mateo Valero (ICPADS, 2009)

An efficient software cache for H.264 motion compensation. - Arnaldo Azevedo; Ben H. H. Juurlink (SoC, 2009)

Instruction-Level Fault Tolerance Configurability. - Demid Borodin; Ben H. H. Juurlink; Said Hamdioui; Stamatis Vassiliadis (J. Signal Process. Syst., 2009)

Leakage-Aware Multiprocessor Scheduling. - Pepijn J. de Langen; Ben H. H. Juurlink (J. Signal Process. Syst., 2009)

Parallel Scalability of Video Decoders. - Cor Meenderinck; Arnaldo Azevedo; Ben H. H. Juurlink; Mauricio Alvarez 001; Alex Ramírez (J. Signal Process. Syst., 2009)

Protective redundancy overhead reduction using instruction vulnerability factor. - Demid Borodin; Ben H. H. Juurlink (Conf. Computing Frontiers, 2010)

Instruction precomputation with memoization for fault detection. - Demid Borodin; Ben H. H. Juurlink (DATE, 2010)

A Case for Hardware Task Management Support for the StarSS Programming Model. - Cor Meenderinck; Ben H. H. Juurlink (DSD, 2010)

Extending the Cell SPE with Energy Efficient Branch Prediction. - Martijn Briejer; Cor Meenderinck; Ben H. H. Juurlink (Euro-Par (1), 2010)

Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine. - Chi Ching Chi; Ben H. H. Juurlink; Cor Meenderinck (ICS, 2010)

A Multidimensional Software Cache for Scratchpad-Based Systems. - Arnaldo Azevedo; Ben H. H. Juurlink (Int. J. Embed. Real Time Commun. Syst., 2010)

The SARC Architecture. - Alex Ramírez; Felipe Cabarcas; Ben H. H. Juurlink; Mauricio Alvarez-Mesa; Friman Sánchez; Arnaldo Azevedo; Cor Meenderinck; Catalin Bogdan Ciobanu; Sebastián Isaza; Georgi Gaydadjiev (IEEE Micro, 2010)

An Instruction to Accelerate Software Caches. - Arnaldo Azevedo; Ben H. H. Juurlink (ARCS, 2011)

Composable local memory organisation for streaming applications on embedded MPSoCs. - Jude Angelo Ambrose; Anca Mariana Molnos; Andrew Nelson 001; Sorin Cotofana; Kees Goossens; Ben H. H. Juurlink (Conf. Computing Frontiers, 2011)

Nexus: Hardware Support for Task-Based Programming. - Cor Meenderinck; Ben H. H. Juurlink (DSD, 2011)

Implications of Merging Phases on Scalability of Multi-core Architectures. - Madhavan Manivannan; Ben H. H. Juurlink; Per Stenström (ICPP, 2011)

A QHD-capable parallel H.264 decoder. - Chi Ching Chi; Ben H. H. Juurlink (ICS, 2011)

Poster: implications of merging phases on scalability of multi-core architectures. - Madhavan Manivannan; Ben H. H. Juurlink; Per Stenström (ICS, 2011)

Multi-Core - the Future of Embedded Systems. - Ben H. H. Juurlink (MBMV, 2011)

A Highly Scalable Parallel Implementation of H.264. - Arnaldo Azevedo; Ben H. H. Juurlink; Cor Meenderinck; Andrei Sergeevich Terechko; Jan Hoogerbrugge; Mauricio Alvarez 001; Alex Ramírez; Mateo Valero (Trans. High Perform. Embed. Archit. Compil., 2011)

A Predictor-Based Power-Saving Policy for DRAM Memories. - Gervin Thomas; Karthik Chandrasekar 001; Benny Akesson; Ben H. H. Juurlink; Kees Goossens (DSD, 2012)

An Optimized Parallel IDCT on Graphics Processing Units. - Biao Wang 001; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink (Euro-Par Workshops, 2012)

Parallel video decoding in the emerging HEVC standard. - Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink; Valeri George; Thomas Schierl (ICASSP, 2012)

Improving the parallelization efficiency of HEVC decoding. - Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink; Valeri George; Thomas Schierl (ICIP, 2012)

Hardware-Based Task Dependency Resolution for the StarSs Programming Model. - Tamer Dallou; Ben H. H. Juurlink (ICPP Workshops, 2012)

SynZEN: A hybrid TTA/VLIW architecture with a distributed register file. - Stefan Hauser; Nico Moser; Ben H. H. Juurlink (NORCHIP, 2012)

Programming parallel embedded and consumer applications in OpenMP superscalar. - Michael Andersch; Chi Ching Chi; Ben H. H. Juurlink (PPoPP, 2012)

Using OpenMP superscalar for parallelization of embedded and consumer applications. - Michael Andersch; Chi Ching Chi; Ben H. H. Juurlink (ICSAMOS, 2012)

Amdahl's law for predicting the future of multicores considered harmful. - Ben H. H. Juurlink; Cor Meenderinck (SIGARCH Comput. Archit. News, 2012)

Parallel Scalability and Efficiency of HEVC Parallelization Approaches. - Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink; Gordon Clare; Félix Henry; Stéphane Pateux; Thomas Schierl (IEEE Trans. Circuits Syst. Video Technol., 2012)

Scalable Parallel Programming Applied to H.264/AVC Decoding. - Ben H. H. Juurlink; Mauricio Alvarez-Mesa; Chi Ching Chi; Arnaldo Azevedo; Cor Meenderinck; Alex Ramírez (Springer, 2012)

HEVC performance and complexity for 4K video. - Benjamin Bross; Valeri George; Mauricio Alvarez-Mesa; Tobias Mayer 001; Chi Ching Chi; Jens Brandenburg; Thomas Schierl; Detlev Marpe; Ben H. H. Juurlink (ICCE-Berlin, 2013)

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator. - Jan Lucas; Sohan Lal; Michael Andersch; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ISPASS, 2013)

Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis. - Chi Ching Chi; Mauricio Alvarez-Mesa; Jan Lucas; Ben H. H. Juurlink; Thomas Schierl (J. Signal Process. Syst., 2013)

A generic implementation of a quantified predictor on FPGAs. - Gervin Thomas; Ahmed Elhossini; Ben H. H. Juurlink (ACM Great Lakes Symposium on VLSI, 2014)

An Integrated Hardware-Software Approach to Task Graph Management. - Nina Engelhardt; Tamer Dallou; Ahmed Elhossini; Ben H. H. Juurlink (HPCC/CSS/ICESS, 2014)

GPGPU workload characteristics and performance analysis. - Sohan Lal; Jan Lucas; Michael Andersch; Mauricio Alvarez-Mesa; Ahmed Elhossini; Ben H. H. Juurlink (ICSAMOS, 2014)

TACO: A scheduling scheme for parallel applications on multicore architectures. - Jan Hendrik Schönherr; Ben H. H. Juurlink; Jan Richling (Sci. Program., 2014)

Low-Power High-Efficiency Video Decoding using General-Purpose Processors. - Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ACM Trans. Archit. Code Optim., 2014)

An Efficient and Flexible FPGA Implementation of a Face Detection System. - Hichem Ben Fekih; Ahmed Elhossini; Ben H. H. Juurlink (ARC, 2015)

Multi/many-core programming: where are we standing? - Jerónimo Castrillón; Lothar Thiele; Lars Schor; Weihua Sheng; Ben H. H. Juurlink; Mauricio Alvarez-Mesa; Angela Pohl; Ralph Jessenberger; Victor Reyes; Rainer Leupers (DATE, 2015)

High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis. - Matthias Göbel 001; Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (FCCM, 2015)

An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only). - Hichem Ben Fekih; Ahmed Elhossini; Ben H. H. Juurlink (FPGA, 2015)

Nexus#: A Distributed Hardware Task Manager for Task-Based Programming Models. - Tamer Dallou; Nina Engelhardt; Ahmed Elhossini; Ben H. H. Juurlink (IPDPS, 2015)

Optimizing HEVC CABAC Decoding with a Context Model Cache and Application-Specific Prefetching. - Philipp Habermann; Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ISM, 2015)

On latency in GPU throughput microarchitectures. - Michael Andersch; Jan Lucas; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ISPASS, 2015)

Reducing HEVC encoding complexity using two-stage motion estimation. - Gabriel Cebrián-Márquez; Chi Ching Chi; José Luis Martínez 001; Pedro Cuenca 001; Mauricio Alvarez-Mesa; Sergio Sanz Rodríguez; Ben H. H. Juurlink (VCIP, 2015)

Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency. - Jan Lucas; Michael Andersch; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ACM Trans. Archit. Code Optim., 2015)

SIMD Acceleration for HEVC Decoding. - Chi Ching Chi; Mauricio Alvarez-Mesa; Benjamin Bross; Ben H. H. Juurlink; Thomas Schierl (IEEE Trans. Circuits Syst. Video Technol., 2015)

Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL. - Biao Wang 001; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink (IEEE Trans. Circuits Syst. Video Technol., 2015)

The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision. - Maurice Peemen; Runbin Shi; Sohan Lal; Ben H. H. Juurlink; Bart Mesman; Henk Corporaal (DATE, 2016)

FPGA based hardware accelerator for KAZE feature extraction algorithm. - Lester Kalms; Ahmed Elhossini; Ben H. H. Juurlink (FPT, 2016)

ALUPower: Data Dependent Power Consumption in GPUs. - Jan Lucas; Ben H. H. Juurlink (MASCOTS, 2016)

Efficient HEVC decoder for heterogeneous CPU with GPU systems. - Biao Wang 001; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink; Diego F. de Souza; Aleksandar Ilic; Nuno Roma; Leonel Sousa (MMSP, 2016)

An evaluation of current SIMD programming models for C++. - Angela Pohl; Biagio Cosenza; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink (WPMVP@PPoPP, 2016)

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. - Matthias Göbel 001; Ahmed Elhossini; Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ARC, 2017)

Static optimization in PHP 7. - Nikita Popov; Biagio Cosenza; Ben H. H. Juurlink; Dmitry Stogov (CC, 2017)

Enabling GPU software developers to optimize their applications - The LPGPU2 approach. - Ben H. H. Juurlink; Jan Lucas; Nadjib Mammeri; Georgios Keramidas; Katerina Pontzolkova; Ignacio Aransay; Chrysa Kokkala; Martyn Bliss; Andrew Richards (DASIP, 2017)

A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign. - Matthias Göbel 001; Ahmed Elhossini; Ben H. H. Juurlink (DSD, 2017)

Syntax Element Partitioning for high-throughput HEVC CABAC decoding. - Philipp Habermann; Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (ICASSP, 2017)

Autotuning Stencil Computations with Structural Ordinal Regression Learning. - Biagio Cosenza; Juan José Durillo; Stefano Ermon; Ben H. H. Juurlink (IPDPS, 2017)

E^2MC: Entropy Encoding Based Memory Compression for GPUs. - Sohan Lal; Jan Lucas; Ben H. H. Juurlink (IPDPS, 2017)

Stencil Autotuning with Ordinal Regression: Extended Abstract. - Biagio Cosenza; Juan José Durillo; Stefano Ermon; Ben H. H. Juurlink (SCOPES, 2017)

The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract. - Ben H. H. Juurlink; Jan Lucas; Nadjib Mammeri; Martyn Bliss; Georgios Keramidas; Chrysa Kokkala; Andrew Richards (SCOPES, 2017)

Application-Specific Cache and Prefetching for HEVC CABAC Decoding. - Philipp Habermann; Chi Ching Chi; Mauricio Alvarez-Mesa; Bernardus Juurlink (IEEE Multim., 2017)

GPU Parallelization of HEVC In-Loop Filters. - Biao Wang 001; Diego F. de Souza; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink; Aleksandar Ilic; Nuno Roma; Leonel Sousa (Int. J. Parallel Program., 2017)

Local memory-aware kernel perforation. - Daniel Maier 002; Biagio Cosenza; Ben H. H. Juurlink (CGO, 2018)

Cost Modelling for Vectorization on ARM. - Angela Pohl; Biagio Cosenza; Ben H. H. Juurlink (CLUSTER, 2018)

Optimal DC/AC data bus inversion coding. - Jan Lucas; Sohan Lal; Ben H. H. Juurlink (DATE, 2018)

OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations. - Biagio Cosenza; Nikita Popov; Ben H. H. Juurlink; Paul Richmond; Mozhgan Kabiri Chimeh; Carmine Spagnuolo; Gennaro Cordasco; Vittorio Scarano (Euro-Par, 2018)

VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs. - Nadjib Mammeri; Ben H. H. Juurlink (IISWC, 2018)

An Application-Specific Memory Management Unit for FPGA-SoCs. - Matthias Goebel 001; Ilja Behnke; Ahmed Elhossini; Ben H. H. Juurlink (IPDPS Workshops, 2018)

Accelerating the RICH Particle Detector Algorithm on Intel Xeon Phi. - Christina Quast; Angela Pohl; Biagio Cosenza; Ben H. H. Juurlink; Rainer Schwemmer (PDP, 2018)

Control Flow Vectorization for ARM NEON. - Angela Pohl; Biagio Cosenza; Ben H. H. Juurlink (SCOPES, 2018)

Performance evaluation of implicit and explicit SIMDization. - Hossein Amiri; Asadollah Shahbahrami; Angela Pohl; Ben H. H. Juurlink (Microprocess. Microsystems, 2018)

Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU. - Biao Wang 001; Diego F. de Souza; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben H. H. Juurlink; Aleksandar Ilic; Nuno Roma; Leonel Sousa (Signal Process. Image Commun., 2018)

MEMPower: Data-Aware GPU Memory Power Model. - Jan Lucas; Ben H. H. Juurlink (ARCS, 2019)

SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs. - Sohan Lal; Jan Lucas; Ben H. H. Juurlink (DATE, 2019)

Predictable GPUs Frequency Scaling for Energy and Performance. - Kaijie Fan; Biagio Cosenza; Ben H. H. Juurlink (ICPP, 2019)

Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC. - Matthias Goebel 001; Kai Norman Clasen; Robert Drehmel; Ben H. H. Juurlink (HPCS, 2019)

Approximating Memory-bound Applications on Mobile GPUs. - Daniel Maier 002; Nadjib Mammeri; Biagio Cosenza; Ben H. H. Juurlink (HPCS, 2019)

Performance Counters based Power Modeling of Mobile GPUs using Deep Learning. - Nadjib Mammeri; Markus Neu; Sohan Lal; Ben H. H. Juurlink (HPCS, 2019)

A Performance Analysis of Vector Length Agnostic Code. - Angela Pohl; Mirko Greese; Biagio Cosenza; Ben H. H. Juurlink (HPCS, 2019)

An Efficient Lightweight Framework for Porting Vision Algorithms on Embedded SoCs. - Apurv Ashish; Sohan Lal; Ben H. H. Juurlink (IESS, 2019)

A Bin-Based Bitstream Partitioning Approach for Parallel CABAC Decoding in Next Generation Video Coding. - Philipp Habermann; Chi Ching Chi; Mauricio Alvarez-Mesa; Ben H. H. Juurlink (IPDPS, 2019)

Portable Cost Modeling for Auto-Vectorizers. - Angela Pohl; Biagio Cosenza; Ben H. H. Juurlink (MASCOTS, 2019)

VComputeLib: Enabling Cross-Platform GPGPU on Mobile and Embedded GPUs. - Nadjib Mammeri; Ben H. H. Juurlink (MoMM, 2019)

DenseDisp: Resource-Aware Disparity Map Estimation by Compressing Siamese Neural Architecture. - Mohammad Loni; Ali Zoljodi; Daniel Maier 002; Amin Majd; Masoud Daneshtalab; Mikael Sjödin; Ben H. H. Juurlink; Reza Akbari (CEC, 2020)

Accelerating The Vvc Decoder For Vector Length Agnostic Simd Architectures. - Yassin Kaddar; Angela Pohl; Ben H. H. Juurlink (ICME, 2020)

Efficient Wavefront Parallel Processing for HEVC CABAC Decoding. - Philipp Habermann; Bernardus Juurlink; C. C. Chi; Mauricio Alvarez-Mesa (PDP, 2020)

A Quantitative Study of Locality in GPU Caches. - Sohan Lal; Ben H. H. Juurlink (SAMOS, 2020)

Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels. - Kaijie Fan; Biagio Cosenza; Ben H. H. Juurlink (Comput., 2020)

Vectorization cost modeling for NEON, AVX and SVE. - Angela Pohl; Biagio Cosenza; Ben H. H. Juurlink (Perform. Evaluation, 2020)

QSLC: Quantization-Based, Low-Error Selective Approximation for GPUs. - Sohan Lal; Jan Lucas; Ben H. H. Juurlink (DATE, 2021)

ALONA: Automatic Loop Nest Approximation with Reconstruction and Space Pruning. - Daniel Maier 002; Biagio Cosenza; Ben H. H. Juurlink (Euro-Par, 2021)

Model-Based Loop Perforation. - Daniel Maier 002; Ben H. H. Juurlink (Euro-Par Workshops, 2021)

Lightweight Dual Modular Redundancy through Approximate Computing. - Gabriel L. Nazar; Pedro H. Kopper; Marcos T. Leipnitz; Ben H. H. Juurlink (SBESC, 2021)

Easy and efficient agent-based simulations with the OpenABL language and compiler. - Biagio Cosenza; Nikita Popov; Ben H. H. Juurlink; Paul Richmond; Mozhgan Kabiri Chimeh; Carmine Spagnuolo; Gennaro Cordasco; Vittorio Scarano (Future Gener. Comput. Syst., 2021)

Effects of Approximate Computing on Workload Characteristics. - Daniel Maier 002; Stefan Schirmeister; Ben H. H. Juurlink (ARCS, 2022)

FLEXDP: flexible frequency scaling for energy-delay product optimization of GPU applications. - Kaijie Fan; Biagio Cosenza; Ben H. H. Juurlink (CF, 2022)

Memory Access Granularity Aware Lossless Compression for GPUs. - Sohan Lal; Manuel Renz; Julian Hartmer; Ben H. H. Juurlink (IPDPS, 2022)

A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads. - Sohan Lal; Sharatchandra Varma Bogaraju; Ben H. H. Juurlink (Int. J. Parallel Program., 2022)