Reply to discussion by B. Keller and R. Nance. - Ben Keller; Richard E. Nance (J. Softw. Maintenance Res. Pract., 1995)

A Pausible Bisynchronous FIFO for GALS Systems. - Ben Keller; Matthew Fojtik; Brucek Khailany (ASYNC, 2015)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A Method for the Systematic Generation of Audit Logs in a Digital Preservation Environment and Its Experimental Implementation In a Production Ready System. - Hao Xu 006; Jason Coposky; Dan Bedard; Jewel Ward; Terrell G. Russell; Arcot Rajasekar; Reagan W. Moore; Ben Keller; Zoey Greer (iPRES, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. - Martin Cochet; Alberto Puggelli; Ben Keller; Brian Zimmer; Milovan Blagojevic; Sylvain Clerc; Philippe Roche; Jean-Luc Autran; Borivoje Nikolic (A-SSCC, 2016)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. - Milovan Blagojevic; Martin Cochet; Ben Keller; Philippe Flatresse; Andrei Vladimirescu; Borivoje Nikolic (VLSI Circuits, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

Energy-Efficient System Design Through Adaptive Voltage Scaling. - Ben Keller (2017)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. - Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Stephen G. Tell; Brian Zimmer; Tezaswi Raja; Kevin Zhou; William J. Dally; Brucek Khailany (ASYNC, 2019)

PRIMAL: Power Inference using Machine Learning. - Yuan Zhou; Haoxing Ren; Yanqing Zhang 002; Ben Keller; Brucek Khailany; Zhiru Zhang (DAC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk). - Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany (ICCAD, 2020)

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. - Vidya A. Chhabria; Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany; Sachin S. Sapatnekar (CoRR, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Accelerating Chip Design With Machine Learning. - Brucek Khailany; Haoxing Ren; Steve Dai; Saad Godil; Ben Keller; Robert Kirby 001; Alicia Klinefelter; Rangharajan Venkatesan; Yanqing Zhang 002; Bryan Catanzaro; William J. Dally (IEEE Micro, 2020)

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. - John Charles Wright; Colin Schmidt 001; Ben Keller; Daniel Palmer Dabbelt; Jaehwa Kwak; Vighnesh Iyer; Nandish Mehta; Pi-Feng Chiu; Stevo Bailey; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2020)

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. - Vidya A. Chhabria; Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany; Sachin S. Sapatnekar (DATE, 2021)

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. - Nathaniel Ross Pinckney; Rangharajan Venkatesan; Ben Keller; Brucek Khailany (ICCAD, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. - Steve Dai; Alicia Klinefelter; Haoxing Ren; Rangharajan Venkatesan; Ben Keller; Nathaniel Ross Pinckney; Brucek Khailany (CoRR, 2021)

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning. - Vidya A. Chhabria; Ben Keller; Yanqing Zhang 002; Sandeep Vollala; Sreedhar Pratty; Haoxing Ren; Brucek Khailany (MLCAD, 2022)

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; William J. Dally; C. Thomas Gray; Brucek Khailany (VLSI Technology and Circuits, 2022)

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression. - Jiaqi Gu 002; Ben Keller; Jean Kossaifi; Anima Anandkumar; Brucek Khailany; David Z. Pan (CoRR, 2022)

AutoDMP: Automated DREAMPlace-based Macro Placement. - Anthony Agnesina; Puranjay Rajvanshi; Tian Yang; Geraldo Pradipta; Austin Jiao; Ben Keller; Brucek Khailany; Haoxing Ren (ISPD, 2023)

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; Charbel Sakr; William J. Dally; C. Thomas Gray; Brucek Khailany (IEEE J. Solid State Circuits, 2023)

GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting. - Sixu Li; Ben Keller; Yingyan Celine Lin; Brucek Khailany (CoRR, 2025)

FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference. - Coleman Hooper; Charbel Sakr; Ben Keller; Rangharajan Venkatesan; Kurt Keutzer; Yakun Sophia Shao; Brucek Khailany (CoRR, 2025)