A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. - Benjamas Tongprasit; Kiyoto Ito; Tadashi Shibata (ISCAS (3), 2005)

Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. - Benjamas Tongprasit; Tadashi Shibata (ISCAS, 2006)

A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing. - Kiyoto Ito; Benjamas Tongprasit; Tadashi Shibata (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)