Evaluation of an FPGA Implementation of the Discrete Element Method. - Benjamin Carrión Schäfer; Steven F. Quigley; Andrew H. C. Chan (FPL, 2001)

Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. - Benjamin Carrión Schäfer; Steven F. Quigley; Andrew H. C. Chan (FCCM, 2002)

Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. - Benjamin Carrión Schäfer; Steven F. Quigley; Andrew H. C. Chan (FPL, 2002)

Acceleration of the discrete element method on a reconfigurable co-processor. - Benjamin Carrión Schäfer (2003)

Temperature-Aware Compilation for VLIWProcessors. - Benjamin Carrión Schäfer; Yongho Lee; Taewhan Kim (RTCSA, 2007)

Hotspots Elimination and Temperature Flattening in VLSI Circuits. - Benjamin Carrión Schäfer; Taewhan Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Autonomous temperature control technique in VLSI circuits through logic replication. - Benjamin Carrión Schäfer; Taewhan Kim (IET Comput. Digit. Tech., 2009)

Design of complex image processing systems in ESL. - Benjamin Carrión Schäfer; Ashish Trambadia; Kazutoshi Wakabayashi (ASP-DAC, 2010)

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. - Shahin Golshan; Eli Bozorgzadeh; Benjamin Carrión Schäfer; Kazutoshi Wakabayashi; Houman Homayoun; Alexander V. Veidenbaum (ISLPED, 2010)

Fixed Point Data Type Modeling for High Level Synthesis. - Benjamin Carrión Schäfer; Yusuke Iguchi; Wataru Takahashi 002; Shingo Nagatani; Kazutoshi Wakabayashi (IEICE Trans. Electron., 2010)

Semi-Automatic Control Unit Generation for Complex VLSI Designs. - Benjamin Carrión Schäfer; Majid Sarrafzadeh (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Design Space Exploration Acceleration Through Operation Clustering. - Benjamin Carrión Schäfer; Kazutoshi Wakabayashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Precision tunable RTL macro-modelling cycle-accurate power estimation. - Benjamin Carrión Schäfer; Kazutoshi Wakabayashi (IET Comput. Digit. Tech., 2011)

Machine learning predictive modelling high-level synthesis design space exploration. - Benjamin Carrión Schäfer; Kazutoshi Wakabayashi (IET Comput. Digit. Tech., 2012)

Divide and conquer high-level synthesis design space exploration. - Benjamin Carrión Schäfer; Kazutoshi Wakabayashi (ACM Trans. Design Autom. Electr. Syst., 2012)

Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. - Benjamin Carrión Schäfer (ASP-DAC, 2014)

HW acceleration of multiple applications on a single FPGA. - Yidi Liu; Benjamin Carrión Schäfer (FPT, 2014)

Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systems. - Benjamin Carrión Schäfer (FPT, 2014)

S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis. - Benjamin Carrión Schäfer; Anushree Mahapatra (IEEE Embed. Syst. Lett., 2014)

Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. - Xiaotong Li; Benjamin Carrión Schäfer (FPL, 2015)

Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support. - Benjamin Carrión Schäfer (IEEE Embed. Syst. Lett., 2015)

Optimization of behavioral IPs in multi-processor system-on-chips. - Yidi Liu; Benjamin Carrión Schäfer (ASP-DAC, 2016)

Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. - Dong Liu; Benjamin Carrión Schäfer (FPL, 2016)

Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs. - Nandeesha Veeranna; Benjamin Carrión Schäfer (FPT, 2016)

On Time Redundancy of Fault Tolerant C-Based MPSoCs. - Anjana Balachandran; Nandeesha Veeranna; Benjamin Carrión Schäfer (ISVLSI, 2016)

Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring. - Jieshi Chen; Benjamin Carrión Schäfer; Ivan Wang Hei Ho (CoRR, 2016)

Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration. - Benjamin Carrión Schäfer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Source Code Error Detection in High-Level Synthesis Functional Verification. - Benjamin Carrión Schäfer (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control. - Benjamin Carrión Schäfer (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study. - Benjamin Carrión Schäfer; David Aledo; Félix Moreno (DSD, 2017)

Learning-based interconnect-aware dataflow accelerator optimization. - Shuangnan Liu; Benjamin Carrión Schäfer (FPL, 2017)

What to Lock?: Functional and Parametric Locking. - Muhammad Yasin; Abhrajit Sengupta; Benjamin Carrión Schäfer; Yiorgos Makris; Ozgur Sinanoglu; Jeyavijayan Rajendran (ACM Great Lakes Symposium on VLSI, 2017)

Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads. - Siyuan Xu; Benjamin Carrión Schäfer (ICCD, 2017)

Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration. - Siyuan Xu; Benjamin Carrión Schäfer; Yidi Liu (ICCD, 2017)

Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. - Nandeesha Veeranna; Benjamin Carrión Schäfer (LATS, 2017)

HW/SW co-design experimental framework using configurable SoCs. - Siyuan Xu; Jianqi Chen; Benjamin Carrión Schäfer (ReConFig, 2017)

Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. - Yidi Liu; Monica Villaverde; Félix Moreno; Benjamin Carrión Schäfer (ReCoSoC, 2017)

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs. - Nandeesha Veeranna; Benjamin Carrión Schäfer (J. Hardw. Syst. Secur., 2017)

S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis. - Nandeesha Veeranna; Benjamin Carrión Schäfer (J. Hardw. Syst. Secur., 2017)

Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments. - Benjamin Carrión Schäfer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques. - Nandeesha Veeranna; Benjamin Carrión Schäfer (IEEE Trans. Emerg. Top. Comput., 2017)

Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies. - Benjamin Carrión Schäfer (ACM Trans. Design Autom. Electr. Syst., 2017)

Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level. - Siyuan Xu; Benjamin Carrión Schäfer (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A machine learning based hard fault recuperation model for approximate hardware accelerators. - Farah Naz Taher; Joseph Callenes-Sloan; Benjamin Carrión Schäfer (DAC, 2018)

Investigation and Optimization of Pin Multiplexing in High-Level Synthesis. - Shuangnan Liu; Francis C. M. Lau 002; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2018)

Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles. - Siyuan Xu; Benjamin Carrión Schäfer (ICCD, 2018)

DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures. - Siyuan Xu; Benjamin Carrión Schäfer (ICCD, 2018)

Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis. - Farah Naz Taher; Mostafa Kishani; Benjamin Carrión Schäfer (IOLTS, 2018)

Control Flow Checking Optimization Based on Regular Patterns Analysis. - Zhiqi Zhu; Joseph Callenes-Sloan; Benjamin Carrión Schäfer (PRDC, 2018)

Accelerating cycle-accurate system-level simulations through behavioral templates. - Anushree Mahapatra; Yidi Liu; Benjamin Carrión Schäfer (Integr., 2018)

Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration. - Shuangnan Liu; Francis C. M. Lau 002; Benjamin Carrión Schäfer (DAC, 2019)

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. - Mustafa M. Shihab; Jingxiang Tian; Gaurav Rajavendra Reddy; Bo Hu; William Swartz; Benjamin Carrión Schäfer; Carl Sechen; Yiorgos Makris (DATE, 2019)

Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis. - Farah Naz Taher; Matthew Joslin; Anjana Balachandran; Zhiqi Zhu; Benjamin Carrión Schäfer (DATE, 2019)

Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis. - Zi Wang 006; Benjamin Carrión Schäfer (DATE, 2019)

Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures. - Maheshwaran Ramesh Babu; Farah Naz Taher; Anjana Balachandran; Benjamin Carrión Schäfer (FCCM, 2019)

Thermal Fingerprinting of FPGA Designs through High-Level Synthesis. - Jianqi Chen; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2019)

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. - Bo Hu; Jingxiang Tian; Mustafa M. Shihab; Gaurav Rajavendra Reddy; William Swartz; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2019)

Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators. - Zhiqi Zhu; Farah Naz Taher; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2019)

Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models. - Siyuan Xu; Benjamin Carrión Schäfer (ICCAD, 2019)

Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation. - Jianqi Chen; Benjamin Carrión Schäfer (ICCD, 2019)

Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design. - Jianqi Chen; Benjamin Carrión Schäfer (ICCD, 2019)

Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure. - Farah Naz Taher; Anjana Balachandran; Benjamin Carrión Schäfer (ICCD, 2019)

Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations. - Siyuan Xu; Benjamin Carrión Schäfer (ICCD, 2019)

Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (FPT, 2019)

Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration. - Anushree Mahapatra; Benjamin Carrión Schäfer (ISCAS, 2019)

VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks. - David Aledo; Benjamin Carrión Schäfer; Félix Moreno (IEICE Trans. Inf. Syst., 2019)

VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration. - Anushree Mahapatra; Benjamin Carrión Schäfer (Integr., 2019)

Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. - Siyuan Xu; Shuangnan Liu; Yidi Liu; Anushree Mahapatra; Monica Villaverde; Félix Moreno; Benjamin Carrión Schäfer (Microprocess. Microsystems, 2019)

Toward Self-Tunable Approximate Computing. - Siyuan Xu; Benjamin Carrión Schäfer (IEEE Trans. Very Large Scale Integr. Syst., 2019)

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. - Jianqi Chen; Monir Zaman; Yiorgos Makris; R. D. Shawn Blanton; Subhasish Mitra; Benjamin Carrión Schäfer (DAC, 2020)

Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration. - Zi Wang 006; Benjamin Carrión Schäfer (DAC, 2020)

An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (DATE, 2020)

Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization. - Zi Wang 006; Jianqi Chen; Benjamin Carrión Schäfer (DATE, 2020)

On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations. - Siyuan Xu; Benjamin Carrión Schäfer (DATE, 2020)

Bespoke Behavioral Processors. - Rohit Sreekumar; Prattay Chowdhury; Benjamin Carrión Schäfer (ICCD, 2020)

Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis. - Zhiqi Zhu; Benjamin Carrión Schäfer (ISCAS, 2020)

Efficient Functional Locking of Behavioral IPs. - Anjana Balachandran; Benjamin Carrión Schäfer (MWSCAS, 2020)

Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows. - Shuangnan Liu; Francis C. M. Lau 002; Benjamin Carrión Schäfer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

High-Level Synthesis Design Space Exploration: Past, Present, and Future. - Benjamin Carrión Schäfer; Zi Wang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. - Jianqi Chen; Benjamin Carrión Schäfer (ASP-DAC, 2021)

Enabling the Design of Behavioral Systems-on-Chip. - Santosh Shetty; Benjamin Carrión Schäfer (DAC, 2021)

Watermarking of Behavioral IPs: A Practical Approach. - Jianqi Chen; Benjamin Carrión Schäfer (DATE, 2021)

Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions. - Zi Wang 006; Benjamin Carrión Schäfer (DATE, 2021)

Unlocking Approximations through Selective Source Code Transformations. - Prattay Chowdhury; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2021)

Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing. - Prattay Chowdhury; Benjamin Carrión Schäfer (ICCD, 2021)

Functional Locking through Omission: From HLS to Obfuscated Design. - Zi Wang 006; Shayan Omais Mohammed; Yiorgos Makris; Benjamin Carrión Schäfer (ICCD, 2021)

Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation. - Yiheng Gao; Benjamin Carrión Schäfer (ISCAS, 2021)

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing. - Zhiqi Zhu; Benjamin Carrión Schäfer (ISCAS, 2021)

BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs. - Prattay Chowdhury; Benjamin Carrión Schäfer (ISLPED, 2021)

Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support. - Qilin Si; M. Imtiaz Rashid; Benjamin Carrión Schäfer (ISVLSI, 2021)

Efficient Hierarchical Post-Silicon Validation and Debug. - Pandy Kalimuthu; Kanad Basu; Benjamin Carrión Schäfer (VLSID, 2021)

Source Code Obfuscation of Behavioral IPs: Challenges and Solutions. - Nandeesha Veeranna; Benjamin Carrion Schafer (Behavioral Synthesis for Hardware Security, 2022)

Optimizing Behavioral Near On-Chip Memory Computing Systems. - Qilin Si; Benjamin Carrion Schafer (ASAP, 2022)

Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. - M. Imtiaz Rashid; Benjamin Carrión Schäfer (ASP-DAC, 2022)

Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling. - Benjamin Carrión Schäfer (ASP-DAC, 2022)

Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration. - M. Imtiaz Rashid; Benjamin Carrion Schafer (ACM Great Lakes Symposium on VLSI, 2022)

Modernizing Hardware Circuits through High-Level Synthesis. - Md. Imtiaz Rashid; Qilin Si; Benjamin Carrión Schäfer (ISCAS, 2022)

Predictive Model Attack for Embedded FPGA Logic Locking. - Prattay Chowdhury; Chaitali Sathe; Benjamin Carrión Schäfer (ISLPED, 2022)

SSSL: Secure Search Space Locking of Behavioral IPs. - Zi Wang 006; Benjamin Carrion Schafer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control. - Prattay Chowdhury; Benjamin Carrión Schäfer (ACM Trans. Design Autom. Electr. Syst., 2022)

Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs. - Zi Wang 006; Benjamin Carrion Schafer (ACM Trans. Design Autom. Electr. Syst., 2022)

Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks. - Prattay Chowdhury; Jorge Castro-Godínez; Benjamin Carrion Schafer (ASP-DAC, 2023)

MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (DATE, 2023)

MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS. - Chaitali Sathe; Yiorgos Makris; Benjamin Carrion Schafer (DATE, 2023)

PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing. - Qilin Si; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2023)

ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors. - Qilin Si; Benjamin Carrión Schäfer (ACM Great Lakes Symposium on VLSI, 2023)

CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis. - M. Imtiaz Rashid; Amir H. Torabi; Benjamin Carrión Schäfer (ISCAS, 2023)

I-TAINTED: Identification of Turmeric Adulteration Using the CavIty PerturbatioN Technique and Technology OptimizED Machine Learning. - Tejinder Kaur; Axel Gamez; José Luis Olvera-Cervantes; Benjamin Carrión Schäfer; Alonso Corona-Chavez (IEEE Access, 2023)

Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. - Pingakshya Goswami; Benjamin Carrión Schäfer; Dinesh Bhatia (Integr., 2023)

Application Specific Approximate Behavioral Processor. - Qilin Si; Prattay Chowdhury; Rohit Sreekumar; Benjamin Carrion Schafer (IEEE Trans. Sustain. Comput., 2023)

Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue. - Baharealsadat Parchamdar; Benjamin Carrión Schäfer (DAC, 2024)

Circumventing Restrictions in Commercial High-Level Synthesis Tools. - Benjamin Carrion Schafer; Chaitali G. Sathe (DATE, 2024)

MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors. - Qilin Si; Benjamin Carrion Schafer (Microprocess. Microsystems, 2024)

Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis. - Md. Imtiaz Rashid; Benjamin Carrión Schäfer (ASP-DAC, 2025)

Efficient and Secure Cloud-based Split Logic Synthesis. - Chaitali Sathe; Yiorgos Makris; Benjamin Carrión Schäfer (ASP-DAC, 2025)

HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs. - Qilin Si; Benjamin Carrión Schäfer (ASP-DAC, 2025)

FREEDOM: FPGA-Based Hardware Redaction Emulator. - Chaital G. Sathe; Yiorgos Makris; Benjamin Carrion Schafer (FCCM, 2025)

EdgeGuard: Robust and Fault-Aware Design for Resilient Edge Computing AI Accelerators. - Sabrina Ahmed; Khaza Anuarul Hoque; Benjamin Carrion Schafer (ACM Great Lakes Symposium on VLSI, 2025)

Improving the Quality of the High-Level Synthesis Estimation Results through Multi-Level Predictive Models. - Victoria Gammenthaler; Benjamin Carrion Schafer (ACM Great Lakes Symposium on VLSI, 2025)

Breaking Behavioral IPs Design Space Lock. - Baharealsadat Parchamdar; Benjamin Carrion Schafer (ACM Great Lakes Symposium on VLSI, 2025)

Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)