28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. - Fady Abouzeid; Sylvain Clerc; Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Damien Croain; Gilles Gasiot; Dimitri Soussan; Philippe Roche (ESSCIRC, 2015)

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Gilles Gasiot; Fady Abouzeid; Sylvain Clerc; Lirida A. B. Naviner; Philippe Roche (IRPS, 2015)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

Partial triplication of a SPARC-V8 microprocessor using fault injection. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (LASCAS, 2015)