Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications. - Shraddha Kothari; Chandan Joishi; Dhirendra Vaidya; Hasan Nejad; Benjamin Colombeau; Swaroop Ganguly; Saurabh Lodha (ESSDERC, 2015)

Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs. - N. Breil; B.-C. Lee; J. Avila Avendano; J. Jewell; M. Vellaikal; E. Newman; E. M. Bazizi; Ashish Pal; L. Liu; Oleg Gluschenkov; A. Greene; S. Mochizuki; et al. (VLSI Technology and Circuits, 2023)

Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling. - Pratik B. Vyas; Ashish Pal; Gregory Costrini; Benjamin Colombeau; Bala Haran; Subi Kengeri; El Mehdi Bazizi (IMW, 2024)

Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery. - Ashish Pal; Sefa Dag; Pratik B. Vyas; Gregory Costrini; Vinod Reddy; Veeraraghavan Basker; Allen Yeong; Benjamin Colombeau; Bala Haran; Subi Kengeri; El Mehdi Bazizi (VLSI Technology and Circuits, 2024)