An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. - Christopher LaFrieda; Benjamin Hill 001; Rajit Manohar (ASYNC, 2010)

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. - Jonathan Tse; Benjamin Hill 001; Rajit Manohar (ASYNC, 2013)

A split-foundry asynchronous FPGA. - Benjamin Hill 001; Robert Karmazin; Carlos Tadeo Ortega Otero; Jonathan Tse; Rajit Manohar (CICC, 2013)

ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. - Carlos Tadeo Ortega Otero; Jonathan Tse; Robert Karmazin; Benjamin Hill 001; Rajit Manohar (ISQED, 2014)

Automatic obfuscated cell layout for trusted split-foundry design. - Carlos Tadeo Ortega Otero; Jonathan Tse; Robert Karmazin; Benjamin Hill 001; Rajit Manohar (HOST, 2015)

Clock Generator with Clock Domain Crossing. - Robert Karmazin; Andrew Lines; Prasad Joshi; Benjamin Hill 001 (ASYNC, 2025)