A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS. - Zhihong Luo; Yeung On Au; Benjamin Lau; Henry Law (J. Circuits Syst. Comput., 2012)

A 0.0129 mm2 DPLL With 1.6 2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS. - Zhihong Luo; Guoxing Wang; Khalil Yousef; Benjamin Lau; Yong Lian 001; Chun-Huat Heng (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Sub-10 mV Power Converter With Fully Integrated Self-Start, MPPT, and ZCS Control for Thermoelectric Energy Harvesting. - Zhihong Luo; Lei Zeng; Benjamin Lau; Yong Lian 001; Chun-Huat Heng (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)