A multiplexer-based digital passive linear counter (PLINCO). - Skyler Weaver; Benjamin P. Hershberg; Pavan Kumar Hanumolu; Un-Ku Moon (ICECS, 2009)

Asynchronous CLS for Zero Crossing based Circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Un-Ku Moon (ICECS, 2010)

PDF folding for stochastic flash ADCs. - Skyler Weaver; Benjamin P. Hershberg; Un-Ku Moon (ICECS, 2010)

A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. - Benjamin P. Hershberg; Skyler Weaver; Un-Ku Moon (ISSCC, 2010)

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp. - Benjamin P. Hershberg; Skyler Weaver; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

Stochastic Flash Analog-to-Digital Conversion. - Skyler Weaver; Benjamin P. Hershberg; Peter Kurahashi; Daniel Knierim; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Binary Access Memory: An optimized lookup table for successive approximation applications. - Benjamin P. Hershberg; Skyler Weaver; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (ISCAS, 2011)

Domino-Logic-Based ADC for Digital Synthesis. - Skyler Weaver; Benjamin P. Hershberg; Nima Maghari; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

The effect of correlated level shifting on noise performance in switched capacitor circuits. - Benjamin P. Hershberg; Tawfiq Musah; Skyler Weaver; Un-Ku Moon (ISCAS, 2012)

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (VLSIC, 2012)

Ring Amplifiers for Switched Capacitor Circuits. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

Parallel gain enhancement technique for switched-capacitor circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Taehwan Oh; Manideep Gande; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (CICC, 2013)

A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. - Benjamin P. Hershberg; Kuba Raczkowski; Kristof Vaesen; Jan Craninckx (ESSCIRC, 2014)

Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells. - Skyler Weaver; Benjamin P. Hershberg; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Real-time RF self-interference cancellation for in-band full duplex. - Tom Vermeulen; Barend van Liempd; Benjamin P. Hershberg; Sofie Pollin (DySPAN, 2015)

In-band full-duplex transceiver technology for 5G mobile networks. - Björn Debaillie; Barend van Liempd; Benjamin P. Hershberg; Jan Craninckx; Kari Rikkinen; D. J. van den Broek; Eric A. M. Klumperink; Bram Nauta (ESSCIRC, 2015)

An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. - Barend van Liempd; Benjamin P. Hershberg; Björn Debaillie; Piet Wambacq; Jan Craninckx (ESSCIRC, 2015)

2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. - Barend van Liempd; Benjamin P. Hershberg; Kuba Raczkowski; Saneaki Ariumi; Udo Karthaus; Karl-Frederik Bink; Jan Craninckx (ISSCC, 2015)

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. - Kuba Raczkowski; Nereo Markulic; Benjamin P. Hershberg; Jan Craninckx (IEEE J. Solid State Circuits, 2015)

20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. - Benjamin P. Hershberg; Barend van Liempd; Xiaoqiang Zhang 008; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2016)

A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (CICC, 2018)

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. - Ewout Martens; Benjamin P. Hershberg; Jan Craninckx (IEEE J. Solid State Circuits, 2018)

A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (ISSCC, 2019)

A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (ISSCC, 2019)

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (VLSI Circuits, 2020)

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ESSCIRC, 2021)

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (VLSI Circuits, 2021)

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. - Kaoru Yamashita; Benjamin P. Hershberg; Kentaro Yoshioka; Hiroki Ishikuro (CICC, 2023)

A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. - Kaoru Yamashita; Benjamin P. Hershberg; Kentaro Yoshioka; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2024)