647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. - Benjamin Stefan Devlin; MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2009)

Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. - Kunihiro Asada; Makoto Ikeda; Benjamin Stefan Devlin; Taku Sogabe (DFT, 2010)

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. - Benjamin Stefan Devlin; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2011)

Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ICECS, 2011)

Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ISLPED, 2011)

A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2011)

Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ASYNC, 2012)

Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (COOL Chips, 2012)

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2012)

Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2013)