Joint sampling-time error and channel skew calibration of time-interleaved ADC in multichannel fiber optic receivers. - Benjamín T. Reyes; Venu Gopinathan; Pablo Sergio Mandolesi; Mario R. Hueda (ISCAS, 2012)

A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system. - Benjamín T. Reyes; German Paulina; Lucas Tealdi; Emanuel Labat; Raul M. Sanchez; Pablo Sergio Mandolesi; Mario Rafael Hueda (LASCAS, 2014)

A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques. - Benjamín T. Reyes; Lucas Tealdi; German Paulina; Emanuel Labat; Raul M. Sanchez; Pablo Sergio Mandolesi; Mario Rafael Hueda (LASCAS, 2014)

An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems. - Raul M. Sanchez; Benjamín T. Reyes; Ariel L. Pola; Mario Rafael Hueda (LASCAS, 2016)

Efficient Estimation and Correction of Mismatch Errors in Time-Interleaved ADCs. - Christian A. Schmidt; Juan E. Cousseau; José Luis Figueroa; Benjamín T. Reyes; Mario R. Hueda (IEEE Trans. Instrum. Meas., 2016)

Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems. - Benjamín T. Reyes; Raul M. Sanchez; Ariel L. Pola; Mario R. Hueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (LASCAS, 2018)

An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. - Leandro Passetti; Agustin C. Galetto; Diego J. Hernando; Damián A. Morero; Benjamín T. Reyes; Mario R. Hueda (ISCAS, 2020)

Background Calibration of Time-Interleaved ADC for Optical Coherent Receivers using Error Backpropagation Techniques. - Fredy Solis; Álvaro Fernandez Bocco; Damián A. Morero; Mario R. Hueda; Benjamín T. Reyes (ISCAS, 2020)

Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. - Leandro Passetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (ISCAS, 2021)

Experimental Evaluation of Backpropagation-Based Background Compensation of TI-ADC with Application to Digital Communication Receivers. - Fredy Solis; Damián A. Morero; Mario R. Hueda; Benjamín T. Reyes (ISCAS, 2021)

8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET. - R. L. Nguyen; A. M. Castrillon; A. Fan; A. Mellati; Benjamín T. Reyes; Cindra Abidin; E. Olsen; F. Ahmad; Geoff Hatcher; J. Chana; Laura Biolato; L. Tse; et al. (ISSCC, 2021)

An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers. - Álvaro Fernandez Bocco; Fredy Solis; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (LASCAS, 2021)

Background Compensation of Frequency Interleaved DAC for Optical Transceivers. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (LASCAS, 2021)

Adaptive Background Compensation of Frequency Interleaved DACs With Application to Coherent Optical Transceivers. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (IEEE Access, 2021)

A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. - Fredy Solis; Álvaro Fernandez Bocco; Agustin C. Galetto; Leandro Passetti; Mario R. Hueda; Benjamín T. Reyes (Int. J. Circuit Theory Appl., 2021)

Backpropagation Based Background Compensation of TI-DAC Errors in High-Speed Transmitters. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (MWSCAS, 2022)

Reduced Complexity Adaptive Background Compensation of Electro-Optic Tx Impairments in Coherent Optical Transceivers. - James Kunst; Juan I. Bonetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (OFC, 2022)

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers. - Fredy Solis; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (IEEE Access, 2022)

Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC. - Leandro Passetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (ICECS, 2023)

Digital Background Compensation of Analog Impairments in Jointly Frequency-Time Interleaved DACs. - Agustin C. Galetto; Juan I. Bonetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (IEEE Access, 2023)

Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers. - Leandro Passetti; Damián A. Morero; Benjamín T. Reyes; Mario R. Hueda (IEEE Access, 2023)

18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm. - F. Ahmad; A. Mellati; A. Fernandez; A. Iyer; A. Fan; Benjamín T. Reyes; Cindra Abidin; Claudio Nani; D. Albano; Fredy Solis; Gabriele Minoia; Geoff Hatcher; et al. (ISSCC, 2024)

18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. - R. L. Nguyen; A. Mellati; A. Fernandez; A. Iyer; A. Fan; Benjamín T. Reyes; Cindra Abidin; Claudio Nani; D. Albano; F. Ahmad; Fredy Solis; Gabriele Minoia; et al. (ISSCC, 2024)

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; D. Albano; C. Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; D. Herbas; et al. (VLSI Technology and Circuits, 2024)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)