Instruction Set Extensions for MPEG-4 Video. - Mladen Berekovic; Hans-Joachim Stolberg; Mark Bernd Kulaczewski; Peter Pirsch; Henning Möller; Holger Runge; Johannes Kneip; Benno Stabernack (J. VLSI Signal Process., 1999)

A system for QOS-enabled MPEG-4 video transmission over Bluetooth for mobile applications. - Corina Scheiter; Rainer Steffen; Markus Zeller; Rudi Knorr; Benno Stabernack; Kai-Immo Wels (ICME, 2003)

Tool-aided performance analysis and optimization of multimedia applications. - Heiko Hübert; Benno Stabernack; Henryk Richter (ESTIMedia, 2004)

Performance and Memory Profiling for Embedded System Design. - Heiko Hübert; Benno Stabernack; Kai-Immo Wels (SIES, 2007)

A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications. - Benno Stabernack; Kai-Immo Wels; Heiko Hübert (IEEE Trans. Consumer Electron., 2007)

Generic algorithms for motion compensation and transformation. - Henryk Richter; Benno Stabernack; Erika Müller (Real-Time Image Processing, 2008)

Power Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling. - Heiko Hübert; Benno Stabernack (MBMV, 2009)

Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures. - Heiko Hübert; Benno Stabernack (IEEE Trans. Circuits Syst. Video Technol., 2009)

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI (Selected papers), 2010)

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI, 2010)

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Ettore Speziale; Diego Melpignano; J. M. Zins; et al. (ReCoSoC, 2011)

A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models. - Jens Brandenburg; Benno Stabernack (ARCS, 2012)

Architectural decomposition of video decoders for many core architectures. - Henryk Richter; Benno Stabernack; Volker Kühn 001 (DASIP, 2012)

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Ettore Speziale; Diego Melpignano; J. M. Zins; et al. (INA-OCMC@HiPEAC, 2012)

Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform. - Jens Brandenburg; Benno Stabernack (DASIP, 2013)

Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing. - Heiko Hübert; Benno Stabernack; Frederik Zilly (IEEE Trans. Circuits Syst. Video Technol., 2013)

A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC. - Jan Hahlbeck; Benno Stabernack (ICCE-Berlin, 2014)

FPGA implementation of a full HD real-time HEVC main profile decoder. - Denis Engelhardt; Jan Moller; Jan Hahlbeck; Benno Stabernack (IEEE Trans. Consumer Electron., 2014)

Hardware implementation of a full HD real-time disparity estimation algorithm. - Martin Werner 004; Benno Stabernack; Christian Riechert (IEEE Trans. Consumer Electron., 2014)

Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format. - Henryk Richter; Benno Stabernack; Volker Kühn 001 (J. Signal Process. Syst., 2014)

Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures. - Jens Brandenburg; Benno Stabernack (DASIP, 2015)

Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support. - Benno Stabernack; Jan Moller; Jan Hahlbeck; Jens Brandenburg (DASIP, 2015)

Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures. - Jens Brandenburg; Benno Stabernack (J. Syst. Archit., 2017)

Modeling the Energy Consumption of the HEVC Decoding Process. - Christian Herglotz; Dominic Springer; Marc Reichenbach; Benno Stabernack; André Kaup (IEEE Trans. Circuits Syst. Video Technol., 2018)

Using Time-of-Flight Sensors for People Counting Applications. - Michal Stec; Viktor Herrmann; Benno Stabernack (DASIP, 2019)

Multi-Sensor-Fusion System for People Counting Applications. - Michal Stec; Viktor Herrmann; Benno Stabernack (SA, 2019)

Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers. - Fritjof Steinert; Niklas Schelten; Anton Schulte; Benno Stabernack (DSD, 2020)

A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution. - Justin Knapheide; Benno Stabernack; Maximilian Kuhnke (FPL, 2020)

A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators. - Niklas Schelten; Fritjof Steinert; Anton Schulte; Benno Stabernack (FPT, 2020)

A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures. - Fritjof Steinert; Philipp Kreowsky; Eric L. Wisotzky; Christian Unger; Benno Stabernack (SmartCloud, 2020)

Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing. - Fritjof Steinert; Justin Knapheide; Benno Stabernack (FPL, 2021)

A Full-Featured FPGA-Based Pipelined Architecture for SIFT Extraction. - Philipp Kreowsky; Benno Stabernack (IEEE Access, 2021)

A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection. - Viktor Herrmann; Justin Knapheide; Fritjof Steinert; Benno Stabernack (DSD, 2022)

Towards an optimal right-turn assistant system to avoid accidents with vulnerable traffic participants. - Michal Stec; Benno Stabernack; Clemens Kubach (MECO, 2022)

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification. - Fritjof Steinert; Benno Stabernack (J. Signal Process. Syst., 2022)

FPGA-Based Network-Attached Accelerators - An Environmental Life Cycle Perspective. - Fritjof Steinert; Benno Stabernack (ARCS, 2023)

Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters. - Justin Knapheide; Philipp Kreowsky; Benno Stabernack (FPL, 2023)

Challenges Using FPGA Clusters for Distributed CNN Training. - Philipp Kreowsky; Justin Knapheide; Benno Stabernack (FPL, 2023)

Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads. - Steffen Christgau; Dylan Everingham; Florian Mikolajczak; Niklas Schelten; Bettina Schnor; Max Schrötter; Benno Stabernack; Fritjof Steinert (SC Workshops, 2023)

A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application. - Niklas Schelten; Fritjof Steinert; Justin Knapheide; Anton Schulte; Benno Stabernack (ACM Trans. Reconfigurable Technol. Syst., 2023)

An Approach Towards Distributed DNN Training on FPGA Clusters. - Philipp Kreowsky; Justin Knapheide; Benno Stabernack (ARCS, 2024)

On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators. - Steffen Christgau; Dylan Everingham; Max Lübke; Marco De Lucia; Danny Puhan; Niklas Schelten; Bettina Schnor; Hannes Signer; Johannes Spazier; Benno Stabernack; Fritjof Steinert; Serhii Yahdzhyiev (IPDPS (Workshops), 2025)