A ultra fast Euclidean division algorithm for prime memory systems. - Benoît Dupont de Dinechin (SC, 1991)

StaCS: a Static Control Superscalar architecture. - Benoît Dupont de Dinechin (MICRO, 1992)

An Introduction to Simplex Scheduling. - Benoît Dupont de Dinechin (IFIP PACT, 1994)

Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers. - Benoît Dupont de Dinechin (LCPC, 1995)

Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates. - Benoît Dupont de Dinechin (LCPC, 1996)

Definition of the F– Extension to Fortran 90. - Robert W. Numrich; Jon L. Steidel; Brian H. Johnson; Benoît Dupont de Dinechin; Gary Elsesser; Greg Fischer; Tom MacDonald (LCPC, 1997)

A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. - Benoît Dupont de Dinechin (PaCT, 1997)

Extending Modulo Scheduling with Memory Reference Merging. - Benoît Dupont de Dinechin (CC, 1999)

Code generator optimizations for the ST120 DSP-MCU core. - Benoît Dupont de Dinechin; François de Ferrière; Christophe Guillon; Artour Stoutchinin (CASES, 2000)

Division by Constant for the ST100 DSP Microprocessor. - Jean-Michel Muller; Arnaud Tisserand; Benoît Dupont de Dinechin; Christophe Monat (IEEE Symposium on Computer Arithmetic, 2005)

SCAN: A Heuristic for Near-Optimal Software Pipelining. - Florent Blachot; Benoît Dupont de Dinechin; Guillaume Huard (Euro-Par, 2006)

Fast liveness checking for ssa-form programs. - Benoit Boissinot; Sebastian Hack; Daniel Grund; Benoît Dupont de Dinechin; Fabrice Rastello (CGO, 2008)

Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. - Benoît Dupont de Dinechin (Euro-Par, 2008)

Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency. - Benoit Boissinot; Alain Darte; Fabrice Rastello; Benoît Dupont de Dinechin; Christophe Guillon (CGO, 2009)

A mixed-precision fused multiply and add. - Nicolas Brunie; Florent de Dinechin; Benoît Dupont de Dinechin (ACSCC, 2011)

A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. - Benoit Boissinot; Florian Brandner; Alain Darte; Benoît Dupont de Dinechin; Fabrice Rastello (APLAS, 2011)

Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. - Sid Ahmed Ali Touati; Frederic Brault; Karine Deschinkel; Benoît Dupont de Dinechin (ACM Trans. Embed. Comput. Syst., 2011)

K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph. - Bruno Bodin; Alix Munier Kordon; Benoît Dupont de Dinechin (ICSAMOS, 2012)

Efficient liveness computation using merge sets and DJ-graphs. - Dibyendu Das 005; Benoît Dupont de Dinechin; Ramakrishna Upadrasta (ACM Trans. Archit. Code Optim., 2012)

Periodic schedules for Cyclo-Static Dataflow. - Bruno Bodin; Alix Munier Kordon; Benoît Dupont de Dinechin (ESTIMedia, 2013)

A clustered manycore processor architecture for embedded and accelerated applications. - Benoît Dupont de Dinechin; Renaud Ayrignac; Pierre-Edouard Beaucamps; Patrice Couvert; Benoit Ganne; Pierre Guironnet de Massas; François Jacquet; Samuel Jones; Nicolas Morey Chaisemartin; Frédéric Riss; Thierry Strudel (HPEC, 2013)

Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor. - Pascal Aubry; Pierre-Edouard Beaucamps; Frédéric Blanc 001; Bruno Bodin; Sergiu Carpov; Loïc Cudennec; Vincent David; Philippe Dore; Paul Dubrulle; Benoît Dupont de Dinechin; François Galea; Thierry Goubier; et al. (ICCS, 2013)

A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor. - Benoît Dupont de Dinechin; Pierre Guironnet de Massas; Guillaume Lager; Clément Léger; Benjamin Orgogozo; Jérôme Reybert; Thierry Strudel (ICCS, 2013)

Scheduling an interval ordered precedence graph with communication delays and a limited number of processors. - Alix Munier Kordon; Fadi Kacem; Benoît Dupont de Dinechin; Lucian Finta (RAIRO Oper. Res., 2013)

Using the SSA-Form in a Code Generator. - Benoît Dupont de Dinechin (CC, 2014)

Time-critical computing on a single-chip massively parallel processor. - Benoît Dupont de Dinechin; Duco van Amstel; Marc Poulhiès; Guillaume Lager (DATE, 2014)

Guaranteed Services of the NoC of a Manycore Processor. - Benoît Dupont de Dinechin; Yves Durand; Duco van Amstel; Alexandre Ghiti (NoCArc@MICRO, 2014)

Converging to periodic schedules for cyclic scheduling problems with resources and deadlines. - Benoît Dupont de Dinechin; Alix Munier Kordon (Comput. Oper. Res., 2014)

The shift to multicores in real-time and safety-critical systems. - Selma Saidi; Rolf Ernst; Sascha Uhrig; Henrik Theiling; Benoît Dupont de Dinechin (CODES+ISSS, 2015)

Implementation of a Fast Fourier transform algorithm onto a manycore processor. - Julien Hascoet; Jean-François Nezan; Andrew Ensor; Benoît Dupont de Dinechin (DASIP, 2015)

Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. - Benoît Dupont de Dinechin (Hot Chips Symposium, 2015)

MPI communication on MPPA Many-core NoC: design, modeling and performance issues. - Minh Quan Ho; Bernard Tourancheau; Christian Obrecht; Benoît Dupont de Dinechin; Jérôme Reybert (PARCO, 2015)

Optimal and fast throughput evaluation of CSDF. - Bruno Bodin; Alix Munier Kordon; Benoît Dupont de Dinechin (DAC, 2016)

Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. - Georgia Giannopoulou; Nikolay Stoimenov; Pengcheng Huang 001; Lothar Thiele; Benoît Dupont de Dinechin (Real Time Syst., 2016)

Hierarchical Dataflow Model for efficient programming of clustered manycore processors. - Julien Hascoet; Karol Desnos; Jean-François Nezan; Benoît Dupont de Dinechin (ASAP, 2017)

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. - Alvise Rigo; Christian Pinto; Kevin Pouget; Daniel Raho; Denis Dutoit; Pierre-Yves Martinez; Chris Doran; Luca Benini; Iakovos Mavroidis; Manolis Marazakis; Valeria Bartsch; Guy Lonsdale; et al. (DSD, 2017)

Asynchronous one-sided communications and synchronizations for a clustered manycore processor. - Julien Hascoët; Benoît Dupont de Dinechin; Pierre Guironnet de Massas; Minh Quan Ho (ESTIMedia, 2017)

Network-on-chip service guarantees on the kalray MPPA-256 bostan processor. - Benoît Dupont de Dinechin; Amaury Graillat (AISTECS@HiPEAC, 2017)

Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors. - Minh Quan Ho; Christian Obrecht; Bernard Tourancheau; Benoît Dupont de Dinechin; Julien Hascoet (IPCCC, 2017)

Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor. - Benoît Dupont de Dinechin; Amaury Graillat (NoCArc@MICRO, 2017)

Parallel code generation of synchronous programs for a many-core architecture. - Amaury Graillat; Matthieu Moy; Pascal Raymond; Benoît Dupont de Dinechin (DATE, 2018)

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. - Hugo Miomandre; Julien Hascoët; Karol Desnos; Kevin J. M. Martin; Benoît Dupont de Dinechin; Jean-François Nezan (PARMA-DITAM@HiPEAC, 2018)

A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore. - Julien Hascoet; Benoît Dupont de Dinechin; Karol Desnos; Jean-François Nezan (HPEC, 2018)

Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus. - Benoît Dupont de Dinechin (NOCS, 2018)

DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. - Georgia Giannopoulou; Peter Poplavko; Dario Socci; Pengcheng Huang 001; Nikolay Stoimenov; Paraskevas Bourgos; Lothar Thiele; Marius Bozga; Saddek Bensalem; Sylvain Girbal; Madeleine Faugère; Romain Soulat; et al. (Des. Autom. Embed. Syst., 2018)

Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor. - Benoît Dupont de Dinechin (DAC, 2019)

Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip. - Amaury Graillat; Claire Maiza; Matthieu Moy; Pascal Raymond; Benoît Dupont de Dinechin (RTNS, 2019)

A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. - Matheus Schuh; Claire Maiza; Joël Goossens; Pascal Raymond; Benoît Dupont de Dinechin (RTSS, 2020)

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. - Marc Boyer; Amaury Graillat; Benoît Dupont de Dinechin; Jörn Migge (Perform. Evaluation, 2020)

Engineering a Manycore Processor for Edge Computing. - Benoît Dupont de Dinechin (MECO, 2021)

Distortion Approximation of a Compressed Softmax Layer. - Diana Resmerita; Rodrigo Cabral Farias; Benoît Dupont de Dinechin; Lionel Fillatre (SSP, 2021)

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities. - Marco Cococcioni; Federico Rossi 003; Emanuele Ruffaldi; Sergio Saponara; Benoît Dupont de Dinechin (IEEE Signal Process. Mag., 2021)

SSA Form and Code Generation. - Benoît Dupont de Dinechin (SSA-based Compiler Design, 2022)

A Posit8 Decompression Operator for Deep Neural Network Inference. - Orégane Desrentes; Diana Resmerita; Benoît Dupont de Dinechin (CoNGA, 2022)

Computing In-Place FFTs with SIMD Lane Slicing. - Benoît Dupont de Dinechin (HPEC, 2022)

Exact Fused Dot Product Add Operators. - Orégane Desrentes; Benoît Dupont de Dinechin; Florent de Dinechin (ARITH, 2023)

Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning. - Orégane Desrentes; Benoît Dupont de Dinechin; Julien Le Maire (DSD, 2023)

In-Place Multicore SIMD Fast Fourier Transforms. - Benoît Dupont de Dinechin; Julien Hascoët; Orégane Desrentes (HPEC, 2023)

Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator. - Orégane Desrentes; Benoît Dupont de Dinechin; Florent de Dinechin (ARITH, 2025)

Architecting Value Prediction around In-Order Execution. - Pierre Ravenel; Arthur Perais; Benoît Dupont de Dinechin; Frédéric Pétrot (HPCA, 2025)