Testing of Glue Logic Interconnects Using Boundary Scan Architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Janusz Rajski; Benoit Nadeau-Dostie (ITC, 1989)

A new procedure for weighted random built-in self-test. - Fidel Muradali; Vinod K. Agarwal; Benoit Nadeau-Dostie (ITC, 1990)

Serial Interfacing for Embedded-Memory Testing. - Benoit Nadeau-Dostie; Allan Silburt; Vinod K. Agarwal (IEEE Des. Test Comput., 1990)

ScanBIST: A Multi-frequency Scan-based BIST Method. - Benoit Nadeau-Dostie; Dwayne Burek; Abu S. M. Hassan (ITC, 1992)

Scan testing of latch arrays. - Michael M. Y. Hui; Benoit Nadeau-Dostie (VTS, 1992)

BIST of PCB interconnects using boundary-scan architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Benoit Nadeau-Dostie; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM. - Allan L. Silburt; Richard S. Phillips; G. F. Randall Gibson; Steven W. Wood; Armin G. Bluschke; James S. Fujimoto; Stephen P. Kornachuk; Benoit Nadeau-Dostie; Rajesh K. Verma; Peter M. J. Diedrich (IEEE J. Solid State Circuits, 1993)

ScanBist: A Multifrequency Scan-Based BIST Method. - Benoit Nadeau-Dostie; Dwayne Burek; Abu S. M. Hassan (IEEE Des. Test Comput., 1994)

A New Hardware Fault Insertion Scheme for System Diagnostics Verification. - Benoit Nadeau-Dostie; Harry Hulvershorn; Saman Adham (ITC, 1995)

Built-In Self-Test: Assuring System Integrity. - Bernd Könemann; Ben Bennetts; Najmi T. Jarwala; Benoit Nadeau-Dostie (Computer, 1996)

An embedded technique for at-speed interconnect testing. - Benoit Nadeau-Dostie; Jean-Francois Cote; Harry Hulvershorn; Stephen Pateras (ITC, 1999)

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. - Samir Boubezari; Eduard Cerny; Bozena Kaminska; Benoit Nadeau-Dostie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. - Stephen K. Sunter; Benoit Nadeau-Dostie (ITC, 2002)

A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. - Saman Adham; Benoit Nadeau-Dostie (MTDT, 2004)

OCI: Open Compression Interface. - Bruce Cory; Rohit Kapur; Mick Tegethoff; Mark Kassab; Brion L. Keller; Kee Sup Kim; Dwayne Burek; Steven F. Oakland; Benoit Nadeau-Dostie (ITC, 2006)

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. - Benoit Nadeau-Dostie; Kiyoshi Takeshita; Jean-Francois Cote (ITC, 2008)

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. - Joon-Sung Yang; Benoit Nadeau-Dostie; Nur A. Touba (DFT, 2009)

Test point insertion using functional flip-flops to drive control points. - Joon-Sung Yang; Benoit Nadeau-Dostie; Nur A. Touba (ITC, 2009)

Improved Core Isolation and Access for Hierarchical Embedded Test. - Benoit Nadeau-Dostie; Saman Adham; Russell Abbott 002 (IEEE Des. Test Comput., 2009)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Test generator with preselected toggling for low power built-in self-test. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Benoit Nadeau-Dostie (VTS, 2012)

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. - Joon-Sung Yang; Nur A. Touba; Benoit Nadeau-Dostie (IEEE Trans. Computers, 2012)

Timing-Aware ATPG. - Mark Kassab; Benoit Nadeau-Dostie; Xijiang Lin (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Low-Power Programmable PRPG With Test Compression Capabilities. - Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Adapting an industrial memory BIST solution for testing CAMs. - Jais Abraham; Uttam Garg; Glenn Colón-Bonet; Ramesh Sharma; Chennian Di; Benoit Nadeau-Dostie; Etienne Racine; Martin Keim (ITC-Asia, 2017)

Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions. - Venkat Yellapragada; Suresh Raman; Banadappa Shivaray; Luc Romain; Benoit Nadeau-Dostie; Martin Keim; Jean-Francois Cote; Albert Au; Giri Podichetty; Ashok Anbalan (ITC-Asia, 2018)

MBIST Support for Reliable eMRAM Sensing. - Jongsin Yun; Benoit Nadeau-Dostie; Martin Keim; Cyrille Dray; El Mehdi Boujamaa (ETS, 2020)

Memory repair logic sharing techniques and their impact on yield. - Benoit Nadeau-Dostie; Luc Romain (ITC, 2020)

MBIST Supported Multi Step Trim for Reliable eMRAM Sensing. - Jongsin Yun; Benoit Nadeau-Dostie; Martin Keim; Lori Schramm; Cyrille Dray; El Mehdi Boujamaa; Khushal Gelda (ITC, 2020)

Configurable BISR Chain For Fast Repair Data Loading. - Wei Zou; Benoit Nadeau-Dostie (ITC, 2022)

Transitioning eMRAM from Pilot Project to Volume Production. - Cyrille Dray; Khushal Gelda; Benoit Nadeau-Dostie; Wei Zou; Luc Romain; Jongsin Yun; Harshitha Kodali; Lori Schramm; Martin Keim (ITC, 2023)

Combining Built-In Redundancy Analysis with ECC for Memory Testing. - Luc Romain; Paul-Patrick Nordmann; Benoit Nadeau-Dostie; Lori Schramm; Martin Keim (ETS, 2024)