Detailed routing by sparse grid graph and minimum-area-captured path search. - Gengjie Chen; Chak-Wa Pui; Haocheng Li; Jingsong Chen; Bentian Jiang; Evangeline F. Y. Young (ASP-DAC, 2019)

A fast machine learning-based mask printability predictor for OPC acceleration. - Bentian Jiang; Hang Zhang 010; Jinglei Yang; Evangeline F. Y. Young (ASP-DAC, 2019)

FIT: Fill Insertion Considering Timing. - Bentian Jiang; Xiaopeng Zhang 009; Ran Chen 001; Gengjie Chen; Peishan Tu; Wei Li 159; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2019)

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. - Haocheng Li; Gengjie Chen; Bentian Jiang; Jingsong Chen; Evangeline F. Y. Young (ICCAD, 2019)

CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. - Bentian Jiang; Jingsong Chen; Jinwei Liu; Lixin Liu; Fangzhou Wang; Xiaopeng Zhang 009; Evangeline F. Y. Young (ICCAD, 2020)

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. - Bentian Jiang; Lixin Liu; Yuzhe Ma; Hang Zhang 010; Bei Yu 001; Evangeline F. Y. Young (ICCAD, 2020)

Building up End-to-end Mask Optimization Framework with Self-training. - Bentian Jiang; Xiaopeng Zhang 009; Lixin Liu; Evangeline F. Y. Young (ISPD, 2021)

Partition and place finite element model on wafer-scale engine. - Jinwei Liu; Xiaopeng Zhang 009; Shiju Lin; Xinshi Zang; Jingsong Chen; Bentian Jiang; Martin D. F. Wong; Evangeline F. Y. Young (DAC, 2022)

A2-ILT: GPU accelerated ILT with spatial attention mechanism. - Qijing Wang; Bentian Jiang; Martin D. F. Wong; Evangeline F. Y. Young (DAC, 2022)

CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. - Bentian Jiang; Jingsong Chen; Jinwei Liu; Lixin Liu; Fangzhou Wang; Xiaopeng Zhang 009; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. - Bentian Jiang; Lixin Liu; Yuzhe Ma; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. - Bentian Jiang; Xinshi Zang; Martin D. F. Wong; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. - Shiju Lin; Bentian Jiang; Weihua Sheng; Evangeline F. Y. Young (DAC, 2024)

Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. - Lixin Liu; Tianji Liu; Bentian Jiang; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)