Background calibration of time-interleaved ADC using direct derivative information. - Benwei Xu; Yun Chiu (ISCAS, 2013)

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. - Yuan Zhou 011; Benwei Xu; Yun Chiu (VLSIC, 2014)

A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM. - Shuang Zhu; Benwei Xu; Bo Wu 009; Kiran Soppimath; Yun Chiu (CICC, 2015)

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. - Yuan Zhou 011; Benwei Xu; Yun Chiu (IEEE J. Solid State Circuits, 2015)

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. - Benwei Xu; Yun Chiu (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. - Bo Wu 009; Shuang Zhu; Benwei Xu; Yun Chiu (ISSCC, 2016)

A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. - Benwei Xu; Yuan Zhou 011; Yun Chiu (VLSI Circuits, 2016)

A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR. - Bo Wu 009; Shuang Zhu; Benwei Xu; Yun Chiu (IEEE J. Solid State Circuits, 2016)

A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM. - Shuang Zhu; Benwei Xu; Bo Wu 009; Kiran Soppimath; Yun Chiu (IEEE J. Solid State Circuits, 2016)

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. - Hongda Xu; Yongda Cai; Ling Du; Yuan Zhou 011; Benwei Xu; Datao Gong; Jingbo Ye; Yun Chiu (ISSCC, 2017)

An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration. - Sudipta Sarkar; Benwei Xu; Brian Elies; Yun Chiu (MWSCAS, 2017)

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. - Benwei Xu; Yuan Zhou 011; Yun Chiu (IEEE J. Solid State Circuits, 2017)

A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. - Hongda Xu; Hai Huang 010; Yongda Cai; Ling Du; Yuan Zhou 011; Benwei Xu; Datao Gong; Jingbo Ye; Yun Chiu (IEEE J. Solid State Circuits, 2019)

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. - Yuan Zhou 011; Benwei Xu; Yun Chiu (IEEE J. Solid State Circuits, 2019)