Placement for Wafer-Scale Deep Learning Accelerator. - Benzheng Li; Qi Du; Dingcheng Liu; Jingchong Zhang; Gengjie Chen; Hailong You (ASP-DAC, 2021)

High quality hypergraph partitioning for logic emulation. - Benzheng Li; Zhongdong Qi; Zhengguang Tang; Xiyi He; Hailong You (Integr., 2022)

ASSURER: A PPA-friendly Security Closure Framework for Physical Design. - Guangxin Guo; Hailong You; Zhengguang Tang; Benzheng Li; Cong Li; Xiaojue Zhang (ASP-DAC, 2023)

Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs. - Benzheng Li; Xi Zhang; Hailong You; Zhongdong Qi; Yuming Zhang (ACM Trans. Design Autom. Electr. Syst., 2023)

An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints. - Benzheng Li; Hailong You; Shunyang Bi; Yuming Zhang (DATE, 2024)

MaPart: An Efficient Multi-FPGA System-Aware Hypergraph Partitioning Framework. - Benzheng Li; Shunyang Bi; Hailong You; Zhongdong Qi; Guangxin Guo; Richard Sun; Yuming Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)