A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS. - Beomsup Kim; David N. Helman; Paul R. Gray (IEEE J. Solid State Circuits, 1990)

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS. - Yuh-Min Lin; Beomsup Kim; Paul R. Gray (IEEE J. Solid State Circuits, 1991)

Optical MMSE gear-shifting algorithm for the fast synchronization of DPLL. - Beomsup Kim (ISCAS, 1993)

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. - Beomsup Kim; Todd C. Weigandt; Paul R. Gray (ISCAS, 1994)

Analysis of Timing Jitter in CMOS Ring Oscillators. - Todd C. Weigandt; Beomsup Kim; Paul R. Gray (ISCAS, 1994)

A digital audio signal processor for cellular phone application. - Jeongsik Yang; Chanhong Park; Beomsup Kim (ASP-DAC, 1995)

Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications. - Byungjin Chun; Beomsup Kim; Yong Hong Lee (ISCAS, 1995)

Optimal loop bandwidth design for low noise PLL applications. - Kyoohyun Lim; Seung Hee Choi; Beomsup Kim (ASP-DAC, 1997)

A Digital Phase-Locked Loop with Variable Loop Gains Derived from RLS Method. - Byungjin Chun; Seung Hee Choi; Beomsup Kim (ICC (1), 1997)

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. - Seog-Jun Lee; Beomsup Kim; Kwyro Lee (IEEE J. Solid State Circuits, 1997)

A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. - Seog-Jun Lee; Beomsup Kim; Kwyro Lee (IEEE J. Solid State Circuits, 1997)

Design of variable loop gains of dual-loop DPLL. - Byungjin Chun; Yong Hoon Lee; Beomsup Kim (IEEE Trans. Commun., 1997)

Dual-loop Digital PLL Design for Adaptive Clock Recovery. - Tae Hun Kim; Beomsup Kim (ASP-DAC, 1998)

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. - Chang-Hyun Kim; Jung-Hwa Lee; J. B. Lee; Beomsup Kim; C. S. Park; Sang-Bo Lee; S. Y. Lee; C. W. Park; J. G. Roh; Hyoung Sik Nam; D. Y. Kim; D. Y. Lee; et al. (IEEE J. Solid State Circuits, 1998)

16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. - Tae Hun Kim; Jeongsik Yang; Kyoo Hyun Lim; Jin Wook Kim; Jeong Eun Lee; Hyoung Sik Nam; Young Gon Kim; Jeong Pyo Kim; Sangjin Byun; Bae Sung Kwon; Beomsup Kim (ASP-DAC, 1999)

A low-noise, 900-MHz VCO in 0.6-μm CMOS. - Chan-Hong Park; Beomsup Kim (IEEE J. Solid State Circuits, 1999)

Non-Data-Aided Timing Recovery Algorithm for pi/4-OPSK Modulated Signals. - Beomsup Kim; Joonsuk Lee; Seung Hee Choi; Jun Mo Koo; Byung Jun Min (ICC (1), 2000)

A low-jitter mixed-mode DLL for high-speed DRAM applications. - Jae Joon Kim; Sang-Bo Lee; Tae-Sung Jung; Chang-Hyun Kim; Soo-In Cho; Beomsup Kim (IEEE J. Solid State Circuits, 2000)

A low-noise fast-lock phase-locked loop with adaptive bandwidth control. - Joonsuk Lee; Beomsup Kim (IEEE J. Solid State Circuits, 2000)

A low-noise phase-locked loop design by loop bandwidth optimization. - Kyoohyun Lim; Chan-Hong Park; Dal-Soo Kim; Beomsup Kim (IEEE J. Solid State Circuits, 2000)

Digital timing synchronization with jitter reduction technique for cap-based VDSL system. - Yongchul Song; Kyehyung Lee; Beomsup Kim (ICASSP, 2001)

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. - Chan-Hong Park; Ook Kim; Beomsup Kim (IEEE J. Solid State Circuits, 2001)

A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. - Sung-Ho Wang; Jeongpyo Kim; Joonsuk Lee; Hyoung Sik Nam; Young Gon Kim; Jae Hoon Shim; Hyung Ki Ahn; Seok Kang; Bong Hwa Jeong; Jin-Hong Ahn; Beomsup Kim (IEEE J. Solid State Circuits, 2001)

A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-μm CMOS. - Yongchul Song; Beomsup Kim (ESSCIRC, 2003)

A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. - Hyung Ki Ahn; In-Cheol Park; Beomsup Kim (ISCAS (1), 2003)

A hybrid delta-sigma modulator with adaptive calibration. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (ISCAS (1), 2003)

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. - Sangjin Byun; Chan-Hong Park; Yongchul Song; Sung-Ho Wang; Cormac S. G. Conroy; Beomsup Kim (IEEE J. Solid State Circuits, 2003)

Low-jitter digital timing recovery techniques for CAP-based VDSL applications. - Yongchul Song; Beomsup Kim (IEEE J. Solid State Circuits, 2003)

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. - Yongchul Song; Beomsup Kim (IEEE J. Solid State Circuits, 2004)

A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR. - Yongchul Song; Beomsup Kim (IEEE J. Solid State Circuits, 2004)

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. - Yongchul Song; Beomsup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band. - Seok Kang; Beomsup Kim (IEICE Trans. Electron., 2005)

Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators. - Jaesang Lim; Jaejoon Kim; Beomsup Kim (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications. - Jaesang Lim; Yongchul Song; Jeong Pyo Kim; Beomsup Kim (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. - Jinwook Kim; Jeongsik Yang; Sangjin Byun; Hyunduk Jun; Jeongkyu Park; Cormac S. G. Conroy; Beomsup Kim (IEEE J. Solid State Circuits, 2005)

A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE J. Solid State Circuits, 2005)

Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE J. Solid State Circuits, 2005)

Hybrid ΣΔ modulators with adaptive calibration. - Jae Hoon Shim; In-Cheol Park; Beomsup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation. - Shen Wang; Dong Sam Ha; Beomsup Kim; Vipul Chawla (CICC, 2011)

Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two. - Shen Wang; Vipul Chawla; Dong Sam Ha; Beomsup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. - Yashar Rajavi; Mohammad Mahdi Ghahramani; Alireza Khalili; Amirpouya Kavousian; Beomsup Kim; Michael P. Flynn (IEEE J. Solid State Circuits, 2017)