Single-chip 4×500-MBd CMOS transceiver. - Albert X. Widmer; Kevin R. Wrenner; Herschel A. Ainspan; Ben Parker; Pierre Austruy; Bernard Brezzo; Anne-Marie Haen; John F. Ewen; Mehmet Soyuer; Alain Blanc; Jean-Claude Abbiate; Alina Deutsch; et al. (IEEE J. Solid State Circuits, 1996)

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. - Jae-sun Seo; Bernard Brezzo; Yong Liu 023; Benjamin D. Parker; Steven K. Esser; Robert K. Montoye; Bipin Rajendran; José A. Tierno; Leland Chang; Dharmendra S. Modha; Daniel J. Friedman (CICC, 2011)

High-Throughput, Lossless Data Compresion on FPGAs. - Bharat Sukhwani; Bülent Abali; Bernard Brezzo; Sameh W. Asaad (FCCM, 2011)

Database analytics acceleration using FPGAs. - Bharat Sukhwani; Hong Min; Mathew Thoennes; Parijat Dube; Balakrishna Iyer; Bernard Brezzo; Donna Dillenberger; Sameh W. Asaad (PACT, 2012)

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. - Sameh W. Asaad; Ralph Bellofatto; Bernard Brezzo; Chuck Haymes; Mohit Kapur; Benjamin D. Parker; Thomas Roewer; Proshanta Saha; Todd Takken; José A. Tierno (FPGA, 2012)

Efficient in-system RTL verification and debugging using FPGAs (abstract only). - Proshanta Saha; Chuck Haymes; Ralph Bellofatto; Bernard Brezzo; Mohit Kapur; Sameh W. Asaad (FPGA, 2012)

Large Payload Streaming Database Sort and Projection on FPGAs. - Bharat Sukhwani; Mathew Thoennes; Hong Min; Parijat Dube; Bernard Brezzo; Sameh W. Asaad; Donna Dillenberger (SBAC-PAD, 2013)

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with 100× Speedup in Time-to-Solution and 100, 000× Reduction in Energy-to-Solution. - Andrew S. Cassidy; Rodrigo Alvarez-Icaza; Filipp Akopyan; Jun Sawada; John V. Arthur; Paul Merolla; Pallab Datta; Marc González Tallada; Brian Taba; Alexander Andreopoulos; Arnon Amir; Steven K. Esser; et al. (SC, 2014)

Database Analytics: A Reconfigurable-Computing Approach. - Bharat Sukhwani; Hong Min; Mathew Thoennes; Parijat Dube; Bernard Brezzo; Sameh W. Asaad; Donna Dillenberger (IEEE Micro, 2014)

A Hardware/Software Approach for Database Query Acceleration with FPGAs. - Bharat Sukhwani; Mathew Thoennes; Hong Min; Parijat Dube; Bernard Brezzo; Sameh W. Asaad; Donna Dillenberger (Int. J. Parallel Program., 2015)

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. - Filipp Akopyan; Jun Sawada; Andrew Cassidy; Rodrigo Alvarez-Icaza; John V. Arthur; Paul Merolla; Nabil Imam; Yutaka Y. Nakamura; Pallab Datta; Gi-Joon Nam; Brian Taba; Michael P. Beakes; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)