Design of radiofrequency stages for a high rate digital modem. - J.-Ph. Lambert; Abbas Dandache; Fabrice Monteiro; Bernard Lepley (ICECS, 1998)

A high-speed parallel DSP architecture dedicated to digital modem applications. - S. Philip; Fabrice Monteiro; Abbas Dandache; Bernard Lepley (ICECS, 1998)

Design of a selective digital filter for a DAVIC compliant modem. - Abbas Dandache; Fabrice Monteiro; Bernard Lepley (ICECS, 2000)

A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code. - T. Vallino; Abbas Dandache; Jean-Paul Delahaye; Fabrice Monteiro; Bernard Lepley (IOLTW, 2000)

A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division. - Fabrice Monteiro; Abbas Dandache; Amine M'sir; Bernard Lepley (ICECS, 2001)

Fast Configurable Polynomial Division for Error Control Coding Applications. - Fabrice Monteiro; Abbas Dandache; Bernard Lepley (IOLTW, 2001)

A High Speed Encoder for Recursive Systematic Convolutive Codes. - Amine M'sir; Fabrice Monteiro; Abbas Dandache; Bernard Lepley (IOLTW, 2002)

A methodology to design a multimedia processor core. - Abbas Ramazani; Fabrice Monteiro; Abbas Dandache; Bernard Lepley (ICECS, 2003)

Designing a High Speed Decoder for Cyclic Codes. - Amine M'sir; Fabrice Monteiro; Abbas Dandache; Bernard Lepley (IOLTS, 2004)

Design of a high speed parallel encoder for convolutional codes. - Amine M'sir; Fabrice Monteiro; Abbas Dandache; Bernard Lepley (Microelectron. J., 2004)