Testability analysis of hierarchical finite state machines. - Françoise Martinolle; Jean Claude Geffroy; Bernard Soulas (EURO-DAC, 1991)

A process algebra interpretation of a verification oriented overlanguage of VHDL. - Catherine Bayol; Bernard Soulas; Dominique Borrione; Fulvio Corno; Paolo Prinetto (EURO-DAC, 1994)

System-Level Modeling and Verification: a Comprehensive Design Methodology. - Paolo Camurati; Fulvio Corno; Paolo Prinetto; Catherine Bayol; Bernard Soulas (EDAC-ETC-EUROASIC, 1994)