Bernd Becker

According to our database1, Bernd Becker
  • authored at least 393 papers between 1982 and 2017.
  • has a "Dijkstra number"2 of four.

Awards

IEEE Fellow

IEEE Fellow 2008, "For contributions to the development of algorithms and data structures for testing and verification of integrated circuits".

Timeline

Legend:

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PhD thesis 
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Links

Homepages:

On csauthors.net:

Bibliography

2017
Cost vs. time in stochastic games and Markov automata.
Formal Asp. Comput., 2017

Permissive Finite-State Controllers of POMDPs using Parameter Synthesis.
CoRR, 2017

Motion Planning under Partial Observability using Game-Based Abstraction.
CoRR, 2017

Efficient SAT-based generation of hazard-activated TSOF tests.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

HQSpre - An Effective Preprocessor for QBF and DQBF.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017

From DQBF to QBF by Dependency Elimination.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2017 - 20th International Conference, Melbourne, VIC, Australia, August 28, 2017

Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Evaluating the effectiveness of D-chains in SAT-based ATPG.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Towards mixed structural-functional models for algebraic fault attacks on ciphers.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Specification and verification of security in reconfigurable scan networks.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Best paper.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Sensitized path PUF: A lightweight embedded physical unclonable function.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A Flexible Framework for the Automatic Generation of SBST Programs.
IEEE Trans. VLSI Syst., 2016

Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs.
IEEE Trans. Multi-Scale Computing Systems, 2016

PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization.
IEEE Trans. Computers, 2016

On Metrics to Quantify the Inter-Device Uniqueness of PUFs.
IACR Cryptology ePrint Archive, 2016

Satisfiability Checking meets Symbolic Computation (Project Paper).
CoRR, 2016

Satisfiability Checking and Symbolic Computation.
CoRR, 2016

Satisfiability checking and symbolic computation.
ACM Comm. Computer Algebra, 2016

Effective generation and evaluation of diagnostic SBST programs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.
Proceedings of the 1st Workshop on Satisfiability Checking and Symbolic Computation co-located with 18th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2016), 2016

iHouse: A Voice-Controlled, Centralized, Retrospective Smart Home.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

PackSens: A Condition and Transport Monitoring System Based on an Embedded Sensor Platform.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

Dependency Schemes for DQBF.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

SC2: Satisfiability Checking Meets Symbolic Computation - (Project Paper).
Proceedings of the Intelligent Computer Mathematics - 9th International Conference, 2016

Applying Tailored Formal Methods to X-ATPG.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Known unknowns - Knowledge in the presence of unknowns.
Proceedings of the 17th Latin-American Test Symposium, 2016

SAT-Based Combinational and Sequential Dependency Computation.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Advancing Software Model Checking Beyond Linear Arithmetic Theories.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Revocable Anonymisation in Video Surveillance: A "Digital Cloak of Invisibility".
Proceedings of the Technology and Intimacy: Choice or Coercion, 2016

Digitale Tarnkappe: Anonymisierung in Videoaufnahmen.
Proceedings of the 46. Jahrestagung der Gesellschaft für Informatik, 2016

Accurate ICP-based floating-point reasoning.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Formal verification of secure reconfigurable scan network infrastructure.
Proceedings of the 21th IEEE European Test Symposium, 2016

Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed Parallel #SAT Solving.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

Skolem Functions for DQBF.
Proceedings of the Automated Technology for Verification and Analysis, 2016

On Optimal Power-Aware Path Sensitization.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Transient Reward Approximation for Continuous-Time Markov Chains.
IEEE Trans. Reliability, 2015

Formal Vulnerability Analysis of Security Components.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

High-level Counterexamples for Probabilistic Automata
Logical Methods in Computer Science, 2015

Verification of partial designs using incremental QBF.
AI Commun., 2015

Improving diagnosis resolution of a fault detection test set.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Abstraction-Based Computation of Reward Measures for Markov Automata.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

Modeling Unknown Values in Test and Verification.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Cost vs. Time in Stochastic Games and Markov Automata.
Proceedings of the Dependable Software Engineering: Theories, Tools, and Applications, 2015

Preprocessing for DQBF.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015

Laissez-Faire Caching for Parallel #SAT Solving.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015

Towards Verification of Artificial Neural Networks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Counterexamples for Expected Rewards.
Proceedings of the FM 2015: Formal Methods, 2015

Improving test pattern generation in presence of unknown values beyond restricted symbolic logic.
Proceedings of the 20th IEEE European Test Symposium, 2015

Identification of high power consuming areas with gate type and logic level information.
Proceedings of the 20th IEEE European Test Symposium, 2015

Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.
Proceedings of the 20th IEEE European Test Symposium, 2015

On the automatic generation of SBST test programs for in-field test.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Solving DQBF through quantifier elimination.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Exact Logic and Fault Simulation in Presence of Unknowns.
ACM Trans. Design Autom. Electr. Syst., 2014

Minimal counterexamples for linear-time probabilistic verification.
Theor. Comput. Sci., 2014

Symbolic counterexample generation for large discrete-time Markov chains.
Sci. Comput. Program., 2014

QBF with Soft Variables.
ECEASST, 2014

MeGARA: Menu-based Game Abstraction and Abstraction Refinement of Markov Automata.
Proceedings of the Proceedings Twelfth International Workshop on Quantitative Aspects of Programming Languages and Systems, 2014

Efficient SAT-Based Circuit Initialization for Larger Designs.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

SAT-Based Test Pattern Generation with Improved Dynamic Compaction.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Counterexample Generation for Discrete-Time Markov Models: An Introductory Survey.
Proceedings of the Formal Methods for Executable Software Models, 2014

Accelerating Parametric Probabilistic Verification.
Proceedings of the Quantitative Evaluation of Systems - 11th International Conference, 2014

Implication Graph Compression inside the SMT Solver iSAT3.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Test pattern generation in presence of unknown values based on restricted symbolic logic.
Proceedings of the 2014 International Test Conference, 2014

Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems.
Proceedings of the Hardware and Software: Verification and Testing, 2014

Using interval constraint propagation for pseudo-Boolean constraint solving.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

Variation-aware deterministic ATPG.
Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Mobile Learning mit kontextbezogenen mobilen Diensten in der "KMU Smart Factory": Szenarien und Lösungsansätze für Fertigungsprozesse.
Proceedings of DeLFI Workshops 2014 co-located with 12th e-Learning Conference of the German Computer Society (DeLFI 2014), 2014

An effective approach to automatic functional processor test generation for small-delay faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Using MaxBMC for Pareto-optimal circuit initialization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Efficient SMT-based ATPG for interconnect open defects.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Incremental Encoding and Solving of Cardinality Constraints.
Proceedings of the Automated Technology for Verification and Analysis, 2014

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs.
Information Security Journal: A Global Perspective, 2013

SAT-Based Analysis of Sensitizable Paths.
IEEE Design & Test, 2013

Accelerating Parametric Probabilistic Verification.
CoRR, 2013

Identification of critical variables using an FPGA-based fault injection framework.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

High-Level Counterexamples for Probabilistic Automata.
Proceedings of the Quantitative Evaluation of Systems - 10th International Conference, 2013

Proving QBF-hardness in Bounded Model Checking for Incomplete Designs.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Recent Improvements in the SMT Solver iSAT.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Equivalence Checking for Partial Implementations Revisited.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Stochastic Bounded Model Checking: Bounded Rewards and Compositionality.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Accurate Computation of Sensitizable Paths Using Answer Set Programming.
Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013

Early-life-failure detection using SAT-based ATPG.
Proceedings of the 2013 IEEE International Test Conference, 2013

Equivalence checking of partial designs using dependency quantified Boolean formulae.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

SMILE: Smartphones in der Lehre - ein Rück- und Überblick.
Proceedings of the Informatik 2013, 2013

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.
Proceedings of the Design, Automation and Test in Europe, 2013

Accurate QBF-based test pattern generation in presence of unknown values.
Proceedings of the Design, Automation and Test in Europe, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition.
Proceedings of the Automated Deduction - CADE-24, 2013

Search Space Reduction for Low-Power Test Generation.
Proceedings of the 22nd Asian Test Symposium, 2013

Accurate Multi-cycle ATPG in Presence of X-Values.
Proceedings of the 22nd Asian Test Symposium, 2013

Provably optimal test cube generation using quantified boolean formula solving.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Transient Reward Approximation for Grids, Crowds, and Viruses
CoRR, 2012

The COMICS Tool - Computing Minimal Counterexamples for Discrete-time Markov Chains
CoRR, 2012

SAT-ATPG using preferences for improved detection of complex defect mechanisms.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Minimal Critical Subsystems for Discrete-Time Markov Models.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation).
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Enhanced Integration of QBF Solving Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Functional test of small-delay faults using SAT and Craig interpolation.
Proceedings of the 2012 IEEE International Test Conference, 2012

TSV and DFT cost aware circuit partitioning for 3D-SOCs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Small-delay-fault ATPG with waveform accuracy.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Symbolic Counterexample Generation for Discrete-Time Markov Chains.
Proceedings of the Formal Aspects of Component Software, 9th International Symposium, 2012

On the quality of test vectors for post-silicon characterization.
Proceedings of the 17th IEEE European Test Symposium, 2012

Exact stuck-at fault classification in presence of unknowns.
Proceedings of the 17th IEEE European Test Symposium, 2012

Multi-conditional SAT-ATPG for power-droop testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

#SAT-based vulnerability analysis of security components - A case study.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Verification of partial designs using incremental QBF solving.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

On the optimality of K longest path generation algorithm under memory constraints.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SMILE - Smartphones in Lectures - Initiating a Smartphone-based Audience Response System as a Student Project.
Proceedings of the CSEDU 2012, 2012

The COMICS Tool - Computing Minimal Counterexamples for DTMCs.
Proceedings of the Automated Technology for Verification and Analysis, 2012

ALLQBF Solving by Computational Learning.
Proceedings of the Automated Technology for Verification and Analysis, 2012

Variation-Aware Fault Grading.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Modeling and Mitigating Transient Errors in Logic Circuits.
IEEE Trans. Dependable Sec. Comput., 2011

Parallel SAT Solving in Bounded Model Checking.
J. Log. Comput., 2011

Parallel QBF Solving with Advanced Knowledge Sharing.
Fundam. Inform., 2011

Incremental preprocessing methods for use in BMC.
Formal Methods in System Design, 2011

Variation-aware fault modeling.
SCIENCE CHINA Information Sciences, 2011

Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

Reachability analysis for incomplete networks of Markov decision processes.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Verifying Incomplete Networks of Timed Automata.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

SMT-based Counterexample Generation for Markov Chains.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Estimation of component criticality in early design steps.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Counterexample Generation for Markov Chains Using SMT-Based Bounded Model Checking.
Proceedings of the Formal Techniques for Distributed Systems, 2011

Craig Interpolation in the Presence of Non-linear Constraints.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2011

Towards Variation-Aware Test Methods.
Proceedings of the 16th European Test Symposium, 2011

SAT-based analysis of sensitisable paths.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Proof certificates and non-linear arithmetic constraints.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Integration of orthogonal QBF solving techniques.
Proceedings of the Design, Automation and Test in Europe, 2011

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.
Proceedings of the Design, Automation and Test in Europe, 2011

Integration of an LP Solver into Interval Constraint Propagation.
Proceedings of the Combinatorial Optimization and Applications, 2011

Hierarchical Counterexamples for Discrete-Time Markov Chains.
Proceedings of the Automated Technology for Verification and Analysis, 2011

Efficient SAT-Based Search for Longest Sensitisable Paths.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Fault diagnosis aware ATE assisted test response compaction.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Bounded Fairness for Probabilistic Distributed Algorithms.
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010
Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).
it - Information Technology, 2010

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.
International Journal of Parallel Programming, 2010

Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs.
Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems.
Proceedings of the QEST 2010, 2010

DTMC Model Checking by SCC Reduction.
Proceedings of the QEST 2010, 2010

Bounded Model Checking of Incomplete Networks of Timed Automata.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Correctness Issues of Symbolic Bisimulation Computation for Markov Chains.
Proceedings of the Measurement, 2010

SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Exploiting Different Strategies for the Parallelization of an SMT Solver.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

10271 Abstracts Collection - Verification over discrete-continuous boundaries.
Proceedings of the Verification over discrete-continuous boundaries, 04.07. - 09.07.2010, 2010

Variation-Aware Fault Modeling.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Compositional Dependability Evaluation for STATEMATE.
IEEE Trans. Software Eng., 2009

SUPERB: Simulator utilizing parallel evaluation of resistive bridges.
ACM Trans. Design Autom. Electr. Syst., 2009

PaMiraXT: Parallel SAT Solving with Threads and Message Passing.
JSAT, 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking.
Proceedings of the Verification, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Dependability Engineering of Silent Self-stabilizing Systems.
Proceedings of the Stabilization, 2009

PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing.
Proceedings of the Theory and Applications of Satisfiability Testing, 2009

Picoso - A Parallel Interval Constraint Solver.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

QmiraXT - A Multithreaded QBF Solver.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

ATPG-based grading of strong fault-secureness.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Comparison of knowledge sharing strategies in a parallel QBF solver.
Proceedings of the 2009 International Conference on High Performance Computing & Simulation, 2009

Reducing temperature variability by routing heat pipes.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Dynamic Compaction in SAT-Based ATPG.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Automatic Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

The Demand for Reliability in Probabilistic Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Proceedings of the 2008 IEEE International Test Conference, 2008

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Propositional approximations for bounded model checking of partial circuit designs.
Proceedings of the 26th International Conference on Computer Design, 2008

Selective Hardening in Early Design Steps.
Proceedings of the 13th European Test Symposium, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.
Proceedings of the 13th European Test Symposium, 2008

A study of cognitive resilience in a JPEG compressor.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

On Reducing Circuit Malfunctions Caused by Soft Errors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Probabilistic Model Checking and Reliability of Results.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Resistive Bridging Fault Simulation of Industrial Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Technische Informatik - eine einführende Darstellung.
Oldenbourg, ISBN: 978-3-486-58650-3, 2008

2007
SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme).
it - Information Technology, 2007

Bounded Model Checking with Parametric Data Structures.
Electr. Notes Theor. Comput. Sci., 2007

Power Droop Testing.
IEEE Design & Test of Computers, 2007

Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors
CoRR, 2007

Evolutionary Optimization in Code-Based Test Compression
CoRR, 2007

An Analysis Framework for Transient-Error Tolerance.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Application of Lifting in Partial Design Analysis.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

AVACS -- Automatic Verification and Analysis of Complex Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Identification of Critical Errors in Imaging Applications.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Computation of minimal counterexamples by using black box techniques and symbolic methods.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimization techniques for BDD-based bisimulation computation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

On Combining 01X-Logic and QBF.
Proceedings of the Computer Aided Systems Theory, 2007

On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals.
Proceedings of the Computer Aided Verification, 19th International Conference, 2007

Multithreaded SAT Solving.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. VLSI Syst., 2006

Simulating Resistive-Bridging and Stuck-At Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Orthogonal Hypergraph Drawing for Improved Visibility.
J. Graph Algorithms Appl., 2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it - Information Technology, 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.
J. Electronic Testing, 2006

A Definition and Classification of Timing Anomalies.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Compositional Performability Evaluation for STATEMATE.
Proceedings of the Third International Conference on the Quantitative Evaluation of Systems (QEST 2006), 2006

Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Memory-aware Bounded Model Checking for Linear Hybrid Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Power Droop Testing.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Parallel SAT Solving in Bounded Model Checking.
Proceedings of the Formal Methods: Applications and Technology, 2006

Low-Cost Hardening of Image Processing Applications Against Soft Errors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Minimization of Large State Spaces using Symbolic Branching Bisimulation.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Sigref- A Symbolic Bisimulation Tool Box.
Proceedings of the Automated Technology for Verification and Analysis, 2006

2005
Modeling Feedback Bridging Faults with Non-Zero Resistance.
J. Electronic Testing, 2005

BDDs in a Branch and Cut Framework.
Proceedings of the Experimental and Efficient Algorithms, 4th InternationalWorkshop, 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Optimizing Bounded Model Checking for Linear Hybrid Systems.
Proceedings of the Verification, 2005

Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Speedup Techniques Utilized in Modern SAT Solvers.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Securing Wireless Networks in a University Environment.
Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

Knowledge Sharing in a Microcontroller based Parallel SAT Solver.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

PaMira - A Parallel SAT Solver with Knowledge Sharing.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

On SAT-based Bounded Invariant Checking of Blackbox Designs.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Transient fault characterization in dynamic noisy environments.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Lemma Exchange in a Microcontroller Based Parallel SAT Solver.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface.
Proceedings of the Workshop Proceedings DeLFI 2005 und GMW05, 2005

Evolutionary Optimization in Code-Based Test Compression.
Proceedings of the 2005 Design, 2005

A Family of Logical Fault Models for Reversible Circuits.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Scalable Delay Fault BIST for Use with Low-Cost ATE.
J. Electronic Testing, 2004

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Early Conflict Detection Based BCP for SAT Solving.
Proceedings of the SAT 2004, 2004

PICHAFF2 - A Hierarchical Parallel SAT Solver.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Early Conflict Detection Based SAT Solving.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Placement and routing optimization for circuits derived from BDDs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Orthogonal hypergraph routing for improved visibility.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Automatic test pattern generation for resistive bridging faults.
Proceedings of the 9th European Test Symposium, 2004

Testing for Missing-Gate Faults in Reversible Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Distributed SAT Solver for Microcontroller.
Proceedings of the ARCS 2004, 2004

Parallel SAT Solving with Microcontrollers.
Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004

2003
Exact Routing with Search Space Reduction.
IEEE Trans. Computers, 2003

Pattern-based verification of connections to intellectual property cores.
Integration, 2003

Polynomial Formal Verification of Multipliers.
Formal Methods in System Design, 2003

Multiple Scan Chain Design for Two-Pattern Testing.
J. Electronic Testing, 2003

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.
J. Electronic Testing, 2003

Reducing ATE Cost in System-on-Chip Test.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Cross Reduction for Orthogonal Circuit Visualization.
Proceedings of the International Conference on VLSI, 2003

Conflict-Based Selection of Branching Rules.
Proceedings of the Theory and Applications of Satisfiability Testing, 2003

The Case for 2-POF.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Conflict-based Selection of Branching Rules in SAT-Algorithms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Simulating Resistive Bridging and Stuck-At Faults.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.
Proceedings of the 2003 Design, 2003

2002
On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division.
Formal Methods in System Design, 2002

Equivalence Checking in the Presence of Incompletely Specified Boxes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Symbolic Simulation of Algorithms Specified in HDL.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Sequential n -Detection Criteria: Keep It Simple.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Stop & Go BIST.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Checking Equivalence for Circuits Containing Incompletely Specified Boxes.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Crossing Reduction by Windows Optimization.
Proceedings of the Graph Drawing, 10th International Symposium, 2002

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
J. Electronic Testing, 2001

Multiple Scan Chain Design for Two-Pattern Testing.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Don't Care Minimization of BMDs: Complexity and Algorithms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Checking Equivalence for Partial Implementations.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Supervised Dynamic Recording in Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Exploiting don't cares to minimize *BMDs.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.
Proceedings of the Computational Intelligence, 2001

Multi-objective Optimisation Based on Relation Favour.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2001

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Checking Equivalence for Partial Implementations.
Proceedings of the 38th Design Automation Conference, 2001

Efficient Pattern-Based Verification of Connections to IP Cores .
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

The multiple variable order problem for binary decision diagrams: theory and practical application.
Proceedings of ASP-DAC 2001, 2001

Application of linearly transformed BDDs in sequential verification.
Proceedings of ASP-DAC 2001, 2001

2000
OKFDD minimization by genetic algorithms with application to circuit design.
Integration, 2000

State Traversal guided by Hamming Distance Profiles.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Verification of Designs Containing Black Boxes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Exact switchbox routing with search space reduction.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Minimization of Ordered Pseudo Kronecker Decision Diagrams.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Specialized Hardware for Implementation of Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

k-Layer Straightline Crossing Minimization by Speeding Up Sifting.
Proceedings of the Graph Drawing, 8th International Symposium, 2000

Verification of Designs Containing Black Boxes.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Testability of Circuits Derived from Lattice Diagrams.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

On the Generation of Multiplexer Circuits for Pass Transistor Logic.
Proceedings of the 2000 Design, 2000

Distance driven finite state machine traversal.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Testability of 2-Level AND/EXOR Circuits.
J. Electronic Testing, 1999

Hybrid Fault Simulation for Synchronous Sequential Circuits.
J. Electronic Testing, 1999

Grouping Heuristics for Word-Level Decision Diagrams.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Exact channel routing using symbolic representation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Grouping heuristics for word-level decision diagrams.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Synthesis of Pseudo Kronecker Lattice Diagrams.
Proceedings of the IEEE International Conference On Computer Design, 1999

Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes.
Proceedings of the Computational Intelligence, 1999

Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.
Proceedings of the Digest of Papers: FTCS-29, 1999

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

On Variable Ordering and Decomposition Type Choice in OKFDDs.
IEEE Trans. Computers, 1998

Testing with decision diagrams.
Integration, 1998

Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Word-level decision diagrams, WLCDs and division.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen.
Leitfäden der Informatik, Teubner, ISBN: 978-3-519-02149-0, 1998

Binary Decision Diagrams - Theory and Implementation.
Springer, ISBN: 978-0-7923-8193-8, 1998

1997
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

On the Expressive Power of OKFDDs.
Formal Methods in System Design, 1997

The K*BMD: A Verification Data Structure.
IEEE Design & Test of Computers, 1997

On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Polynomial Formal Verification of Multipliers.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

(Quasi-) Linear Path Delay Fault Tests for Adders.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Manipulation Algorithms for K*BMDs.
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1997

Fault Simulation in Sequential Multi-Valued Logic Networks.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Functional simulation using binary decision diagrams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast and efficient construction of BDDs by reordering based synthesis.
Proceedings of the European Design and Test Conference, 1997

Testability of 2-level AND/EXOR circuits.
Proceedings of the European Design and Test Conference, 1997

Learning heuristics for OKFDD minimization by evolutionary algorithms.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

On the representational power of bit-level and word-level decision diagrams.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.
IEEE Trans. Computers, 1996

On the (non-)resetability of synchronous sequential circuits.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Learning Heuristics for OBDD Minimization by Evolutionary Algorithms.
Proceedings of the Parallel Problem Solving from Nature, 1996

Local Transformations and Robust Dependent Path Delay.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

MORE: an alternative implementation of BDD packages by multi-operand synthesis.
Proceedings of the conference on European design automation, 1996

K*BMDs: A New Data Structure for Verification.
Proceedings of the 1996 European Design and Test Conference, 1996

A Fast Optimal Robust Path Delay Fault Testable Adder.
Proceedings of the 1996 European Design and Test Conference, 1996

AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
On the generation of area-time optimal testable adders.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

On the testability of iterative logic arrays.
Integration, 1995

A Genetic Algorithm for Decomposition Type Choice in OKFDDs.
International Journal on Artificial Intelligence Tools, 1995

On the Relation between BDDs and FDDs.
Inf. Comput., 1995

On local transformations and path delay fault testability.
J. Electronic Testing, 1995

On the application of local circuit transformations with special emphasis on path delay fault testability.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On the Relation Betwen BDDs and FDDs.
Proceedings of the LATIN '95: Theoretical Informatics, 1995

Random Pattern Fault Simulation in Multi-Valued Circuits.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Dynamic minimization of OKFDDs.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

OKFDDs versus OBDDs and OFDDs.
Proceedings of the Automata, Languages and Programming, 22nd International Colloquium, 1995

OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation.
Proceedings of the Digest of Papers: FTCS-25, 1995

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
Proceedings of the 1995 European Design and Test Conference, 1995

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.
Proceedings of the 1995 European Design and Test Conference, 1995

How many decomposition types do we need? [decision diagrams].
Proceedings of the 1995 European Design and Test Conference, 1995

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.
Proceedings of the 32st Conference on Design Automation, 1995

Learning heuristics by genetic algorithms.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A Hybrid Fault Simulator for Synchronous Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Hierarchical Approach to Fault Collapsing.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Fast OFDD based minimization of fixed polarity Reed-Muller expressions.
Proceedings of the Proceedings EURO-DAC'94, 1994

Testability of Circuits Derived from Functional Decision Diagrams.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
Proceedings of the 31st Conference on Design Automation, 1994

1993
FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A BDD - based Algorithm for Computation of Exact Fault Detection Probabilities.
Proceedings of the Digest of Papers: FTCS-23, 1993

On the implementation of an efficient performance driven generator for conditional-sum-adders.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Synthesis for Testability: Binary Decision Diagrams.
Proceedings of the STACS 92, 1992

Some Remarks on the Test Complexity of Iterative Logic Arrays.
Proceedings of the Mathematical Foundations of Computer Science 1992, 1992

A performance driven generator for efficient testable conditional-sum-adders.
Proceedings of the conference on European design automation, 1992

Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up.
Proceedings of the conference on European design automation, 1992

A time optimal robust path-delay-fault self-testable adder.
Proceedings of the conference on European design automation, 1992

1991
Computations over Finite Monoids and their Test Complexity.
Theor. Comput. Sci., 1991

A uniform test approach for RCC-adders.
Fundam. Inform., 1991

Structure based methods for parallel pattern fault simulation in combinational circuits.
Proceedings of the conference on European design automation, 1991

1990
Optimal-Time Multipliers and C-Testability.
Elektronische Informationsverarbeitung und Kybernetik, 1990

Optimal-Time Multipliers and C-Testability.
SPAA, 1990

A graphical system for hierarchical specifications and checkups of VLSI circuits.
Proceedings of the European Design Automation Conference, 1990

1989
Computations over finite monoids and their test complexity.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
How Robust Is The n-Cube?
Inf. Comput., May, 1988

Efficient Testing of Optimal Time Adders.
IEEE Trans. Computers, 1988

On the Construction of Optimal Time Adders (Extended Abstract).
Proceedings of the STACS 88, 1988

Regular Structures and Testing: RCC-Adders.
Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988

1987
Layouts with Wires of Balanced Length
Inf. Comput., April, 1987

On the Optimal Layout of Planar Graphs with Fixed Boundary.
SIAM J. Comput., 1987

An Easily Testable Optimal-Time VLSI-Multiplier.
Acta Inf., 1987

Hierarchical Design Based on a Calculus of Nets.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, June 28, 1987

1986
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform., Forsch. Entwickl., 1986

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform., Forsch. Entwickl., 1986

Efficient Testing of Optimal Time Adders (Extended Abstract).
Proceedings of the Mathematical Foundations of Computer Science 1986, 1986

How Robust Is the n-Cube? (Extended Abstract)
Proceedings of the 27th Annual Symposium on Foundations of Computer Science, 1986

1985
Layouts with Wires of Balanced Length.
Proceedings of the STACS 85, 1985

1983
On the crossing-free, rectangular embedding of weighted graphs in the plane.
Proceedings of the Theoretical Computer Science, 1983

1982
Über die kreuzungsfreie, rechtwinklige Einbettung von gewichteten Graphen in die Ebene.
PhD thesis, 1982


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