Design Validation: Formal Verification vs. Simulation vs. Functional Testing. - Bernd Koenemann; J. Monzel; T. Powell; N. Saxena; K. Wagner (VTS, 1996)

BIST: Advantages or Limitations? - Bernd Koenemann; J. Monzel; T. Powell; N. Saxena; K. Wagner (VTS, 1996)

ATE for VLSI: What Challenges Lie Ahead? - D. Cheung; Bernd Koenemann; S. Nishtala; B. West; D. Wu (VTS, 1997)

EDA in IBM: past, present, and future. - John A. Darringer; Evan E. Davidson; David J. Hathaway; Bernd Koenemann; Mark A. Lavin; Joseph K. Morrell; Khalid Rahmat; Wolfgang Roesner; Erich C. Schanzenbach; Gustavo E. Téllez; Louise Trevillyan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue. - Bill Bottoms; Jim Chung; Bernd Koenemann; Glenn Shirley; Lisa Spainhower (VTS, 2001)

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? - Fidel Muradali; Mike Ricchetti; Bart Vermeulen; Bulent I. Dervisoglu; Bob Gottlieb; Bernd Koenemann; C. J. Clark (VTS, 2002)

STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data. - Bernd Koenemann (Asian Test Symposium, 2003)

Design/process learning from electrical test. - Bernd Koenemann (ICCAD, 2004)

Test In the Era of "What You see Is NOT What You Get". - Bernd Koenemann (ITC, 2004)

DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. - David Abercrombie; Bernd Koenemann; Nagesh Tamarapalli; Srikanth Venkataraman (VLSI Design, 2006)