Hierarchical placement for macrocells: a 'meet in the middle' approach. - Bernhard Eschermann; Wayne Wei-Ming Dai; Ernest S. Kuh; Massoud Pedram (ICCAD, 1988)

PLA based finite state machines using Johnson counters as state memories. - Rainer Amann; Bernhard Eschermann; Utz G. Baitinger (ICCD, 1988)

Optimized synthesis of self-testable finite state machines. - Bernhard Eschermann; Hans-Joachim Wunderlich (FTCS, 1990)

A Unified Approach for the Synthesis of Self-Testable Finite State Machines. - Bernhard Eschermann; Hans-Joachim Wunderlich (DAC, 1991)

Module Generation for AND/XOR Fields (XPLAs). - Jürgen Frößl; Bernhard Eschermann (ICCD, 1991)

Emulation of Scan Paths in Sequential Circuit Synthesis. - Bernhard Eschermann; Hans-Joachim Wunderlich (Fault-Tolerant Computing Systems, 1991)

On Combining Off-Line BIST and On-Line Control Flow Checking. - Bernhard Eschermann (FTCS, 1992)

An implicitly testable boundary scan TAP controller. - Bernhard Eschermann (J. Electron. Test., 1992)

Synthesis and self-test of random logic control units. - Bernhard Eschermann (Integr., 1992)

Optimized synthesis techniques for testable sequential circuits. - Bernhard Eschermann; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Testfreundliche Synthese hochintegrierter Schaltungen - Bernhard Eschermann (1992)

Funktionaler Entwurf digitaler Schaltungen - Methoden und CAD-Techniken. - Bernhard Eschermann (Springer, 1993)

State Assignment for Hardwired VLSI Control Units. - Bernhard Eschermann (ACM Comput. Surv., 1993)

Enhancing on-line testability during synthesis. - Bernhard Eschermann (J. Electron. Test., 1993)

Fail-Safe On-Board Communication for Automatic Train Protection. - Bernhard Eschermann; Hubert D. Kirrmann (GI Jahrestagung, 1994)

Dependability Evaluation of a Computing System for Traction Control of Electrical Locomotives. - Silke Draber; Bernhard Eschermann (EDCC, 1996)