Performance Estimation of Virtual Duplex Systems on Simultaneous Multithreaded Processors. - Bernhard Fechner; Jörg Keller 001; Peter Sobe (IPDPS, 2004)

A Fault-Tolerant Voting Scheme for Multithreaded Environments. - Bernhard Fechner; Jörg Keller 001 (PARELEC, 2004)

Hardware Reliability. - Irene Eusgeld; Bernhard Fechner; Felix Salfner; Max Walter; Philipp Limbourg; Lijun Zhang 001 (Dependability Metrics, 2005)

Dynamic Delay-Fault Injection for Reconfigurable Hardware. - Bernhard Fechner (IPDPS, 2005)

Microcode with Embedded Timing Constraints. - Bernhard Fechner (ARCS Workshops, 2006)

Analysis of checksum-based execution schemes for pipelined processors. - Bernhard Fechner (IPDPS, 2006)

Web server protection by customized instruction set encoding. - Bernhard Fechner; Jörg Keller 001; Andreas Wohlfeld (IPDPS, 2006)

A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments. - Bernhard Fechner (PARELEC, 2006)

A Result Propagation Scheme for Redundant Multithreaded Systems. - Bernhard Fechner (PDPTA, 2006)

Transient Fault Detection in State-Automata. - Bernhard Fechner; Andre Osterloh (DepCoS-RELCOMEX, 2007)

A True Random Number Generator with Built-in Attack Detection. - Bernhard Fechner; Andre Osterloh (DepCoS-RELCOMEX, 2008)

Fault-tolerant static scheduling for grids. - Bernhard Fechner; Udo Hönig; Jörg Keller 001; Wolfram Schiffmann (IPDPS, 2008)

Dynamische Fehlererkennungs- und behebungsmechanismen für verlässliche Mikroprozessoren. - Bernhard Fechner (2008)

Fault-Masking Capabilities of Basic Circuit Structures. - Bernhard Fechner (DepCoS-RELCOMEX, 2009)

A Tool for Dependable and Distributable Presentations. - Bernhard Fechner; Oliver Körber (DepCoS-RELCOMEX, 2009)

Transiente Fehler in Mikroprozessoren: Mechanismen zur Erkennung, Behebung und Tolerierung. - Bernhard Fechner (Vieweg + Teubner, Germany, 2009)

GPU-Based Parallel Signature Scanning and Hash Generation. - Bernhard Fechner (ARCS Workshops, 2010)

A meta-level true random number generator. - Bernhard Fechner; Andre Osterloh (Int. J. Crit. Comput. Based Syst., 2010)

Reliability Bottlenecks in Integrated Parallel Fault-Tolerant Systems. - Bernhard Fechner (ARCS Workshops, 2011)

Fault Localization in NoCs by Timed Heartbeats. - Bernhard Fechner; Arne Garbade; Sebastian Weis; Theo Ungerer (ARCS Workshops, 2012)

Challenges for the manycore era: From dawn to dusk(?). - Bernhard Fechner (HPCS, 2012)

Fault coverage of a timing and control flow checker for hard real-time systems. - Julian Wolf 002; Bernhard Fechner; Theo Ungerer (IOLTS, 2012)

Fine-grained timing and control flow error checking for hard real-time task execution. - Julian Wolf 002; Bernhard Fechner; Sascha Uhrig; Theo Ungerer (SIES, 2012)

A multilevel fault model for integrated parallel fault-tolerant systems. - Bernhard Fechner (Concurr. Comput. Pract. Exp., 2012)

3, 14159... oder die näherungsweise Berechnung von π. - Bernhard Fechner (Inform. Spektrum, 2012)

Fast online error detection and correction with thread signature calculae. - Bernhard Fechner (Microprocess. Microsystems, 2012)

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. - Marco Solinas; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Sylvain Girbal; Daniel Goodman 001; Behram Khan; et al. (DSD, 2013)

Fault detection and tolerance mechanisms for future 1000 core systems. - Bernhard Fechner; Arne Garbade; Sebastian Weis; Theo Ungerer (HPCS, 2013)

Fault Localization in NoCs Exploiting Periodic Heartbeat Messages in a Many-Core Environment. - Arne Garbade; Sebastian Weis; Sebastian Schlingmann; Bernhard Fechner; Theo Ungerer (IPDPS Workshops, 2013)

Impact of Message Based Fault Detectors on Applications Messages in a Network on Chip. - Arne Garbade; Sebastian Weis; Sebastian Schlingmann; Bernhard Fechner; Theo Ungerer (PDP, 2013)

Trust-Enhanced Self-configuration for Organic Computing Systems. - Nizar Msadek; Rolf Kiefhaber; Bernhard Fechner; Theo Ungerer (ARCS, 2014)

TERAFLUX: Harnessing dataflow in next generation teradevices. - Roberto Giorgi; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Rahulkumar Gayatri; Sylvain Girbal; Daniel Goodman 001; et al. (Microprocess. Microsystems, 2014)

Pattern-Based Survey and Categorization of Network Covert Channel Techniques. - Steffen Wendzel; Sebastian Zander; Bernhard Fechner; Christian Herdin (ACM Comput. Surv., 2015)

Architectural Support for Fault Tolerance in a Teradevice Dataflow System. - Sebastian Weis; Arne Garbade; Bernhard Fechner; Avi Mendelson; Roberto Giorgi; Theo Ungerer (Int. J. Parallel Program., 2016)

Anforderungsmanagement in großen IT-Projekten. - Kai Engel; Bernhard Fechner; Alicja Berthold-Kraiczy; Andreas Homrighausen; Ruth Dillhage (Inform. Spektrum, 2018)

Steganography Hiding Patterns: A Brief Review. - Steffen Wendzel; Luca Caviglione; Bernhard Fechner (EICC, 2022)