Transmission gate delay models for circuit optimization. - Veronika Eisele; Bernhard Hoppe; Oliver Kiehl (EURO-DAC, 1990)

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. - Bernhard Hoppe; Gerd Neuendorf; Doris Schmitt-Landsiedel; J. Will Specks (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Pipelined architecture for fast CMOS buffer RAMs. - Doris Schmitt-Landsiedel; Bernhard Hoppe; Gerd Neuendorf; Maria Wurm; Josef Winnerl (IEEE J. Solid State Circuits, 1990)

A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels. - Martin Engels; Bernhard Hoppe; Hermann Meuth; Reiner Peters (ISCAS (5), 1999)

VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. - Ireneusz Janiszewski; Bernhard Hoppe; Hermann Meuth (DAC, 2001)

Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators. - Ireneusz Janiszewski; Bernhard Hoppe; Hermann Meuth (ESM, 2002)

FPGA-Efficient Hybrid LUT/CORDIC Architecture. - Ireneusz Janiszewski; Hermann Meuth; Bernhard Hoppe (FPL, 2004)

FPGA-efficient phase-to-I/Q architecture. - Ireneusz Janiszewski; Hermann Meuth; Bernhard Hoppe (SoCC, 2004)

A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture. - Christian Jakob; A. Th. Schwarzbacher; Bernhard Hoppe; Reiner Peters (DSD, 2007)

A Multichannel Digital Real-Time Correlator as Single FPGA Implementation. - Christian Jakob; A. Th. Schwarzbacher; Bernhard Hoppe; Reiner Peters (DSP, 2007)

Opening a M. Sc. in Electrical Engineering for non-traditional Students. - Anja Lina Müller; Andreas Schwarzbacher; Bernhard Hoppe (Int. J. Adv. Corp. Learn., 2012)