Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. - Bernhard Rohfleisch; Franc Brglez (EDAC-ETC-EUROASIC, 1994)

Logic Clause Analysis for Delay Optimization. - Bernhard Rohfleisch; Bernd Wurth; Kurt Antreich (DAC, 1995)

Reducing Power Dissipation after Technology Mapping by Structural Transformations. - Bernhard Rohfleisch; Alfred Kölbl; Bernd Wurth (DAC, 1996)

Timing driven placement in interaction with netlist transformations. - Guenter Stenz; Bernhard M. Riess; Bernhard Rohfleisch; Frank M. Johannes (ISPD, 1997)

Optimierung von Netzlisten kombinatorischer Schaltungen. - Bernhard Rohfleisch (Shaker, 1997)

Embedded memories in system design - from technology to systems architecture. - Soren Hein; Vijay Nagasamy; Bernhard Rohfleisch; Christoforos E. Kozyrakis; Nikil D. Dutt; Francky Catthoor (ICCAD, 1998)

Performance optimization by interacting netlist transformations andplacement. - Guenter Stenz; Bernhard M. Riess; Bernhard Rohfleisch; Frank M. Johannes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Variation-aware leakage power model extraction for system-level hierarchical power analysis. - Yang Xu 019; Bing Li 005; Ralph Hasholzner; Bernhard Rohfleisch; Christian Haubelt; Jürgen Teich (DATE, 2012)